Lines Matching refs:UIC_ARG_MIB_SEL
34 { UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01, in tc_dwc_g210_setup_40bit_rmmi()
36 { UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19, in tc_dwc_g210_setup_40bit_rmmi()
38 { UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x14, in tc_dwc_g210_setup_40bit_rmmi()
40 { UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6, in tc_dwc_g210_setup_40bit_rmmi()
42 { UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01, in tc_dwc_g210_setup_40bit_rmmi()
44 { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19, in tc_dwc_g210_setup_40bit_rmmi()
46 { UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN0_RX), 4, in tc_dwc_g210_setup_40bit_rmmi()
48 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80, in tc_dwc_g210_setup_40bit_rmmi()
52 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80, in tc_dwc_g210_setup_40bit_rmmi()
54 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03, in tc_dwc_g210_setup_40bit_rmmi()
56 { UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16, in tc_dwc_g210_setup_40bit_rmmi()
58 { UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN0_RX), 0x42, in tc_dwc_g210_setup_40bit_rmmi()
60 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN0_RX), 0xa4, in tc_dwc_g210_setup_40bit_rmmi()
62 { UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01, in tc_dwc_g210_setup_40bit_rmmi()
64 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN0_RX), 0x01, in tc_dwc_g210_setup_40bit_rmmi()
66 { UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28, in tc_dwc_g210_setup_40bit_rmmi()
68 { UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E, in tc_dwc_g210_setup_40bit_rmmi()
70 { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f, in tc_dwc_g210_setup_40bit_rmmi()
72 { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f, in tc_dwc_g210_setup_40bit_rmmi()
91 { UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01, in tc_dwc_g210_setup_20bit_rmmi_lane0()
93 { UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19, in tc_dwc_g210_setup_20bit_rmmi_lane0()
95 { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19, in tc_dwc_g210_setup_20bit_rmmi_lane0()
97 { UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x12, in tc_dwc_g210_setup_20bit_rmmi_lane0()
99 { UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6, in tc_dwc_g210_setup_20bit_rmmi_lane0()
101 { UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01, in tc_dwc_g210_setup_20bit_rmmi_lane0()
103 { UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN0_RX), 2, in tc_dwc_g210_setup_20bit_rmmi_lane0()
105 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80, in tc_dwc_g210_setup_20bit_rmmi_lane0()
109 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03, in tc_dwc_g210_setup_20bit_rmmi_lane0()
111 { UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16, in tc_dwc_g210_setup_20bit_rmmi_lane0()
113 { UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN0_RX), 0x42, in tc_dwc_g210_setup_20bit_rmmi_lane0()
115 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN0_RX), 0xa4, in tc_dwc_g210_setup_20bit_rmmi_lane0()
117 { UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01, in tc_dwc_g210_setup_20bit_rmmi_lane0()
119 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN0_RX), 0x01, in tc_dwc_g210_setup_20bit_rmmi_lane0()
121 { UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28, in tc_dwc_g210_setup_20bit_rmmi_lane0()
123 { UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E, in tc_dwc_g210_setup_20bit_rmmi_lane0()
125 { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f, in tc_dwc_g210_setup_20bit_rmmi_lane0()
148 { UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN1_TX), 0x0d, in tc_dwc_g210_setup_20bit_rmmi_lane1()
150 { UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN1_TX), 0x19, in tc_dwc_g210_setup_20bit_rmmi_lane1()
152 { UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN1_TX), 0x12, in tc_dwc_g210_setup_20bit_rmmi_lane1()
154 { UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6, in tc_dwc_g210_setup_20bit_rmmi_lane1()
159 { UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN1_RX), 0x01, in tc_dwc_g210_setup_20bit_rmmi_lane1()
161 { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN1_RX), 0x19, in tc_dwc_g210_setup_20bit_rmmi_lane1()
163 { UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN1_RX), 2, in tc_dwc_g210_setup_20bit_rmmi_lane1()
165 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN1_RX), 0x80, in tc_dwc_g210_setup_20bit_rmmi_lane1()
167 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN1_RX), 0x03, in tc_dwc_g210_setup_20bit_rmmi_lane1()
169 { UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN1_RX), 0x16, in tc_dwc_g210_setup_20bit_rmmi_lane1()
171 { UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN1_RX), 0x42, in tc_dwc_g210_setup_20bit_rmmi_lane1()
173 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN1_RX), 0xa4, in tc_dwc_g210_setup_20bit_rmmi_lane1()
175 { UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN1_RX), 0x01, in tc_dwc_g210_setup_20bit_rmmi_lane1()
177 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN1_RX), 0x01, in tc_dwc_g210_setup_20bit_rmmi_lane1()
179 { UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN1_RX), 0x28, in tc_dwc_g210_setup_20bit_rmmi_lane1()
181 { UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN1_RX), 0x1E, in tc_dwc_g210_setup_20bit_rmmi_lane1()
183 { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN1_RX), 0x2f, in tc_dwc_g210_setup_20bit_rmmi_lane1()