Lines Matching refs:hba

219 	struct ufs_hba *hba = ufs->hba;  in exynosauto_ufs_post_hce_enable()  local
222 ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL); in exynosauto_ufs_post_hce_enable()
233 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_pre_link() local
240 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); in exynosauto_ufs_pre_link()
242 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i), in exynosauto_ufs_pre_link()
244 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); in exynosauto_ufs_pre_link()
246 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), in exynosauto_ufs_pre_link()
248 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), in exynosauto_ufs_pre_link()
250 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), in exynosauto_ufs_pre_link()
253 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79); in exynosauto_ufs_pre_link()
254 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); in exynosauto_ufs_pre_link()
255 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); in exynosauto_ufs_pre_link()
259 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), in exynosauto_ufs_pre_link()
262 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i), in exynosauto_ufs_pre_link()
265 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i), in exynosauto_ufs_pre_link()
267 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i), in exynosauto_ufs_pre_link()
269 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i), in exynosauto_ufs_pre_link()
273 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1); in exynosauto_ufs_pre_link()
276 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); in exynosauto_ufs_pre_link()
278 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); in exynosauto_ufs_pre_link()
280 ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000); in exynosauto_ufs_pre_link()
288 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_pre_pwr_change() local
291 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); in exynosauto_ufs_pre_pwr_change()
292 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); in exynosauto_ufs_pre_pwr_change()
293 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); in exynosauto_ufs_pre_pwr_change()
301 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_post_pwr_change() local
304 enabled_vh = ufshcd_readl(hba, MHCTRL) & MHCTRL_EN_VH_MASK; in exynosauto_ufs_post_pwr_change()
307 ufshcd_writel(hba, MH_MSG(enabled_vh, MH_MSG_PH_READY), PH2VH_MBOX); in exynosauto_ufs_post_pwr_change()
314 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_pre_link() local
318 exynos_ufs_enable_ov_tm(hba); in exynos7_ufs_pre_link()
320 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17); in exynos7_ufs_pre_link()
322 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff); in exynos7_ufs_pre_link()
323 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00); in exynos7_ufs_pre_link()
325 exynos_ufs_disable_ov_tm(hba); in exynos7_ufs_pre_link()
328 ufshcd_dme_set(hba, in exynos7_ufs_pre_link()
330 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1); in exynos7_ufs_pre_link()
332 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12)); in exynos7_ufs_pre_link()
333 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1); in exynos7_ufs_pre_link()
334 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1); in exynos7_ufs_pre_link()
335 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1); in exynos7_ufs_pre_link()
337 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val); in exynos7_ufs_pre_link()
344 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_link() local
347 exynos_ufs_enable_ov_tm(hba); in exynos7_ufs_post_link()
349 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83); in exynos7_ufs_post_link()
350 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07); in exynos7_ufs_post_link()
351 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i), in exynos7_ufs_post_link()
354 exynos_ufs_disable_ov_tm(hba); in exynos7_ufs_post_link()
356 exynos_ufs_enable_dbg_mode(hba); in exynos7_ufs_post_link()
357 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xbb8); in exynos7_ufs_post_link()
358 exynos_ufs_disable_dbg_mode(hba); in exynos7_ufs_post_link()
374 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_pwr_change() local
377 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_RXPHY_CFGUPDT), 0x1); in exynos7_ufs_post_pwr_change()
380 exynos_ufs_enable_dbg_mode(hba); in exynos7_ufs_post_pwr_change()
381 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 0x1); in exynos7_ufs_post_pwr_change()
382 exynos_ufs_disable_dbg_mode(hba); in exynos7_ufs_post_pwr_change()
420 struct ufs_hba *hba = ufs->hba; in exynos_ufs_get_clk_info() local
421 struct list_head *head = &hba->clk_list_head; in exynos_ufs_get_clk_info()
441 dev_err(hba->dev, "failed to get clk info\n"); in exynos_ufs_get_clk_info()
462 dev_err(hba->dev, "not available pclk range %lu\n", pclk_rate); in exynos_ufs_get_clk_info()
487 struct ufs_hba *hba = ufs->hba; in exynos_ufs_set_pwm_clk_div() local
490 ufshcd_dme_set(hba, in exynos_ufs_set_pwm_clk_div()
496 struct ufs_hba *hba = ufs->hba; in exynos_ufs_calc_pwm_clk_div() local
517 ufshcd_dme_get(hba, UIC_ARG_MIB(CMN_PWM_CLK_CTRL), &clk_idx); in exynos_ufs_calc_pwm_clk_div()
518 dev_err(hba->dev, in exynos_ufs_calc_pwm_clk_div()
571 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_time_attr() local
577 exynos_ufs_enable_ov_tm(hba); in exynos_ufs_config_phy_time_attr()
580 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i), in exynos_ufs_config_phy_time_attr()
582 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i), in exynos_ufs_config_phy_time_attr()
584 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
586 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_15_08, i), in exynos_ufs_config_phy_time_attr()
588 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
590 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_10_08, i), in exynos_ufs_config_phy_time_attr()
592 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_SLEEP_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
594 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_STALL_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
599 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LINERESET_P_VAL, i), in exynos_ufs_config_phy_time_attr()
601 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_07_00, i), in exynos_ufs_config_phy_time_attr()
603 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_11_08, i), in exynos_ufs_config_phy_time_attr()
605 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
607 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_15_08, i), in exynos_ufs_config_phy_time_attr()
609 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
611 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_10_08, i), in exynos_ufs_config_phy_time_attr()
613 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_OV_SLEEP_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
616 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, i), in exynos_ufs_config_phy_time_attr()
620 exynos_ufs_disable_ov_tm(hba); in exynos_ufs_config_phy_time_attr()
625 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_cap_attr() local
629 exynos_ufs_enable_ov_tm(hba); in exynos_ufs_config_phy_cap_attr()
632 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
635 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
638 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
641 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
644 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
647 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
654 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
658 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
663 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
670 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
676 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
682 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
689 exynos_ufs_disable_ov_tm(hba); in exynos_ufs_config_phy_cap_attr()
694 struct ufs_hba *hba = ufs->hba; in exynos_ufs_establish_connt() local
703 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_IDLE); in exynos_ufs_establish_connt()
706 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), DEV_ID); in exynos_ufs_establish_connt()
707 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), TRUE); in exynos_ufs_establish_connt()
708 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), PEER_DEV_ID); in exynos_ufs_establish_connt()
709 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERCPORTID), PEER_CPORT_ID); in exynos_ufs_establish_connt()
710 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTFLAGS), CPORT_DEF_FLAGS); in exynos_ufs_establish_connt()
711 ufshcd_dme_set(hba, UIC_ARG_MIB(T_TRAFFICCLASS), TRAFFIC_CLASS); in exynos_ufs_establish_connt()
712 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED); in exynos_ufs_establish_connt()
735 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_sync_pattern_mask() local
757 exynos_ufs_enable_ov_tm(hba); in exynos_ufs_config_sync_pattern_mask()
760 ufshcd_dme_set(hba, in exynos_ufs_config_sync_pattern_mask()
763 exynos_ufs_disable_ov_tm(hba); in exynos_ufs_config_sync_pattern_mask()
766 static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba, in exynos_ufs_pre_pwr_mode() argument
770 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_pre_pwr_mode()
805 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064); in exynos_ufs_pre_pwr_mode()
806 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224); in exynos_ufs_pre_pwr_mode()
807 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160); in exynos_ufs_pre_pwr_mode()
815 static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba, in exynos_ufs_post_pwr_mode() argument
818 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_post_pwr_mode()
850 dev_info(hba->dev, "Power mode changed to : %s\n", pwr_str); in exynos_ufs_post_pwr_mode()
855 static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba, in exynos_ufs_specify_nexus_t_xfer_req() argument
858 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_specify_nexus_t_xfer_req()
869 static void exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba *hba, in exynos_ufs_specify_nexus_t_tm_req() argument
872 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_specify_nexus_t_tm_req()
893 struct ufs_hba *hba = ufs->hba; in exynos_ufs_phy_init() local
898 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES), in exynos_ufs_phy_init()
900 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES), in exynos_ufs_phy_init()
910 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", in exynos_ufs_phy_init()
925 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_unipro() local
927 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD), in exynos_ufs_config_unipro()
929 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS), in exynos_ufs_config_unipro()
931 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), in exynos_ufs_config_unipro()
956 static int exynos_ufs_setup_clocks(struct ufs_hba *hba, bool on, in exynos_ufs_setup_clocks() argument
959 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_setup_clocks()
977 static int exynos_ufs_pre_link(struct ufs_hba *hba) in exynos_ufs_pre_link() argument
979 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_pre_link()
997 exynos_ufs_setup_clocks(hba, true, PRE_CHANGE); in exynos_ufs_pre_link()
1013 static int exynos_ufs_post_link(struct ufs_hba *hba) in exynos_ufs_post_link() argument
1015 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_post_link()
1025 hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE); in exynos_ufs_post_link()
1026 hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE); in exynos_ufs_post_link()
1030 ufshcd_dme_set(hba, in exynos_ufs_post_link()
1034 exynos_ufs_enable_dbg_mode(hba); in exynos_ufs_post_link()
1035 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_GRANULARITY), in exynos_ufs_post_link()
1037 exynos_ufs_disable_dbg_mode(hba); in exynos_ufs_post_link()
1040 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), in exynos_ufs_post_link()
1044 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), in exynos_ufs_post_link()
1050 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), in exynos_ufs_post_link()
1053 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME), in exynos_ufs_post_link()
1058 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 0); in exynos_ufs_post_link()
1062 dev_warn(hba->dev, in exynos_ufs_post_link()
1119 static inline void exynos_ufs_priv_init(struct ufs_hba *hba, in exynos_ufs_priv_init() argument
1122 ufs->hba = hba; in exynos_ufs_priv_init()
1127 hba->priv = (void *)ufs; in exynos_ufs_priv_init()
1128 hba->quirks = ufs->drv_data->quirks; in exynos_ufs_priv_init()
1131 static int exynos_ufs_init(struct ufs_hba *hba) in exynos_ufs_init() argument
1133 struct device *dev = hba->dev; in exynos_ufs_init()
1180 exynos_ufs_priv_init(hba, ufs); in exynos_ufs_init()
1200 hba->priv = NULL; in exynos_ufs_init()
1204 static int exynos_ufs_host_reset(struct ufs_hba *hba) in exynos_ufs_host_reset() argument
1206 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_host_reset()
1220 dev_err(hba->dev, "timeout host sw-reset\n"); in exynos_ufs_host_reset()
1228 static void exynos_ufs_dev_hw_reset(struct ufs_hba *hba) in exynos_ufs_dev_hw_reset() argument
1230 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_dev_hw_reset()
1237 static void exynos_ufs_pre_hibern8(struct ufs_hba *hba, u8 enter) in exynos_ufs_pre_hibern8() argument
1239 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_pre_hibern8()
1270 static void exynos_ufs_post_hibern8(struct ufs_hba *hba, u8 enter) in exynos_ufs_post_hibern8() argument
1272 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_post_hibern8()
1283 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &cur_mode); in exynos_ufs_post_hibern8()
1285 dev_warn(hba->dev, "%s: power mode change\n", __func__); in exynos_ufs_post_hibern8()
1286 hba->pwr_info.pwr_rx = (cur_mode >> 4) & 0xf; in exynos_ufs_post_hibern8()
1287 hba->pwr_info.pwr_tx = cur_mode & 0xf; in exynos_ufs_post_hibern8()
1288 ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); in exynos_ufs_post_hibern8()
1301 static int exynos_ufs_hce_enable_notify(struct ufs_hba *hba, in exynos_ufs_hce_enable_notify() argument
1304 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_hce_enable_notify()
1315 ret = exynos_ufs_host_reset(hba); in exynos_ufs_hce_enable_notify()
1318 exynos_ufs_dev_hw_reset(hba); in exynos_ufs_hce_enable_notify()
1334 static int exynos_ufs_link_startup_notify(struct ufs_hba *hba, in exynos_ufs_link_startup_notify() argument
1341 ret = exynos_ufs_pre_link(hba); in exynos_ufs_link_startup_notify()
1344 ret = exynos_ufs_post_link(hba); in exynos_ufs_link_startup_notify()
1351 static int exynos_ufs_pwr_change_notify(struct ufs_hba *hba, in exynos_ufs_pwr_change_notify() argument
1360 ret = exynos_ufs_pre_pwr_mode(hba, dev_max_params, in exynos_ufs_pwr_change_notify()
1364 ret = exynos_ufs_post_pwr_mode(hba, dev_req_params); in exynos_ufs_pwr_change_notify()
1371 static void exynos_ufs_hibern8_notify(struct ufs_hba *hba, in exynos_ufs_hibern8_notify() argument
1377 exynos_ufs_pre_hibern8(hba, enter); in exynos_ufs_hibern8_notify()
1380 exynos_ufs_post_hibern8(hba, enter); in exynos_ufs_hibern8_notify()
1385 static int exynos_ufs_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, in exynos_ufs_suspend() argument
1388 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_suspend()
1393 if (!ufshcd_is_link_active(hba)) in exynos_ufs_suspend()
1399 static int exynos_ufs_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) in exynos_ufs_resume() argument
1401 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_resume()
1403 if (!ufshcd_is_link_active(hba)) in exynos_ufs_resume()
1411 static int exynosauto_ufs_vh_link_startup_notify(struct ufs_hba *hba, in exynosauto_ufs_vh_link_startup_notify() argument
1415 ufshcd_set_link_active(hba); in exynosauto_ufs_vh_link_startup_notify()
1416 ufshcd_set_ufs_dev_active(hba); in exynosauto_ufs_vh_link_startup_notify()
1422 static int exynosauto_ufs_vh_wait_ph_ready(struct ufs_hba *hba) in exynosauto_ufs_vh_wait_ph_ready() argument
1431 mbox = ufshcd_readl(hba, PH2VH_MBOX); in exynosauto_ufs_vh_wait_ph_ready()
1444 static int exynosauto_ufs_vh_init(struct ufs_hba *hba) in exynosauto_ufs_vh_init() argument
1446 struct device *dev = hba->dev; in exynosauto_ufs_vh_init()
1462 ret = exynosauto_ufs_vh_wait_ph_ready(hba); in exynosauto_ufs_vh_init()
1470 exynos_ufs_priv_init(hba, ufs); in exynosauto_ufs_vh_init()
1515 struct ufs_hba *hba = platform_get_drvdata(pdev); in exynos_ufs_remove() local
1518 ufshcd_remove(hba); in exynos_ufs_remove()