Lines Matching refs:writel_relaxed
196 writel_relaxed(val, base + SE_IRQ_EN); in geni_se_io_set_mode()
200 writel_relaxed(val, base + SE_GENI_DMA_MODE_EN); in geni_se_io_set_mode()
202 writel_relaxed(0, base + SE_GSI_EVENT_EN); in geni_se_io_set_mode()
211 writel_relaxed(val, base + GENI_CGC_CTRL); in geni_se_io_init()
216 writel_relaxed(val, base + SE_DMA_GENERAL_CFG); in geni_se_io_init()
218 writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL); in geni_se_io_init()
219 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG); in geni_se_io_init()
224 writel_relaxed(0, se->base + SE_GSI_EVENT_EN); in geni_se_irq_clear()
225 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR); in geni_se_irq_clear()
226 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR); in geni_se_irq_clear()
227 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR); in geni_se_irq_clear()
228 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR); in geni_se_irq_clear()
229 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN); in geni_se_irq_clear()
249 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG); in geni_se_init()
250 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG); in geni_se_init()
254 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_init()
258 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); in geni_se_init()
284 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_select_fifo_mode()
289 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); in geni_se_select_fifo_mode()
295 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_fifo_mode()
310 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_select_dma_mode()
315 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); in geni_se_select_dma_mode()
321 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_dma_mode()
471 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0); in geni_se_config_packing()
472 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1); in geni_se_config_packing()
475 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0); in geni_se_config_packing()
476 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1); in geni_se_config_packing()
487 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN); in geni_se_config_packing()
700 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); in geni_se_tx_dma_prep()
701 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L); in geni_se_tx_dma_prep()
702 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H); in geni_se_tx_dma_prep()
703 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); in geni_se_tx_dma_prep()
736 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); in geni_se_rx_dma_prep()
737 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L); in geni_se_rx_dma_prep()
738 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H); in geni_se_rx_dma_prep()
740 writel_relaxed(0, se->base + SE_DMA_RX_ATTR); in geni_se_rx_dma_prep()