Lines Matching refs:reg_base

93 	struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;  in fsl_spi_change_mode()  local
94 __be32 __iomem *mode = &reg_base->mode; in fsl_spi_change_mode()
293 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_bufs() local
298 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE); in fsl_spi_cpu_bufs()
302 mpc8xxx_spi_write_reg(&reg_base->transmit, word); in fsl_spi_cpu_bufs()
311 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_bufs() local
316 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_bufs()
349 mpc8xxx_spi_write_reg(&reg_base->mask, 0); in fsl_spi_bufs()
442 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_setup() local
460 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_setup()
463 cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode); in fsl_spi_setup()
501 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_irq() local
505 u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive); in fsl_spi_cpu_irq()
514 mpc8xxx_spi_read_reg(&reg_base->event)) & in fsl_spi_cpu_irq()
519 mpc8xxx_spi_write_reg(&reg_base->event, events); in fsl_spi_cpu_irq()
525 mpc8xxx_spi_write_reg(&reg_base->transmit, word); in fsl_spi_cpu_irq()
536 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_irq() local
539 events = mpc8xxx_spi_read_reg(&reg_base->event); in fsl_spi_irq()
556 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; in fsl_spi_grlib_cs_control() local
563 slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel); in fsl_spi_grlib_cs_control()
565 mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel); in fsl_spi_grlib_cs_control()
574 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; in fsl_spi_grlib_probe() local
578 capabilities = mpc8xxx_spi_read_reg(&reg_base->cap); in fsl_spi_grlib_probe()
588 mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff); in fsl_spi_grlib_probe()
600 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_probe() local
627 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); in fsl_spi_probe()
628 if (IS_ERR(mpc8xxx_spi->reg_base)) { in fsl_spi_probe()
629 ret = PTR_ERR(mpc8xxx_spi->reg_base); in fsl_spi_probe()
655 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_probe()
658 mpc8xxx_spi_write_reg(&reg_base->mode, 0); in fsl_spi_probe()
659 mpc8xxx_spi_write_reg(&reg_base->mask, 0); in fsl_spi_probe()
660 mpc8xxx_spi_write_reg(&reg_base->command, 0); in fsl_spi_probe()
661 mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff); in fsl_spi_probe()
672 mpc8xxx_spi_write_reg(&reg_base->mode, regval); in fsl_spi_probe()
678 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, in fsl_spi_probe()