Lines Matching refs:reg_val
199 u32 reg_val; in mtk_spi_reset() local
202 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
203 reg_val |= SPI_CMD_RST; in mtk_spi_reset()
204 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
206 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
207 reg_val &= ~SPI_CMD_RST; in mtk_spi_reset()
208 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
218 u32 reg_val; in mtk_spi_set_hw_cs_timing() local
237 reg_val = readl(mdata->base + SPI_CFG0_REG); in mtk_spi_set_hw_cs_timing()
241 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); in mtk_spi_set_hw_cs_timing()
242 reg_val |= (((hold - 1) & 0xffff) in mtk_spi_set_hw_cs_timing()
247 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); in mtk_spi_set_hw_cs_timing()
248 reg_val |= (((setup - 1) & 0xffff) in mtk_spi_set_hw_cs_timing()
254 reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET); in mtk_spi_set_hw_cs_timing()
255 reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); in mtk_spi_set_hw_cs_timing()
259 reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET); in mtk_spi_set_hw_cs_timing()
260 reg_val |= (((setup - 1) & 0xff) in mtk_spi_set_hw_cs_timing()
264 writel(reg_val, mdata->base + SPI_CFG0_REG); in mtk_spi_set_hw_cs_timing()
269 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_set_hw_cs_timing()
270 reg_val &= ~SPI_CFG1_CS_IDLE_MASK; in mtk_spi_set_hw_cs_timing()
271 reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); in mtk_spi_set_hw_cs_timing()
272 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_set_hw_cs_timing()
282 u32 reg_val; in mtk_spi_prepare_message() local
290 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_prepare_message()
292 reg_val |= SPI_CMD_CPHA; in mtk_spi_prepare_message()
294 reg_val &= ~SPI_CMD_CPHA; in mtk_spi_prepare_message()
296 reg_val |= SPI_CMD_CPOL; in mtk_spi_prepare_message()
298 reg_val &= ~SPI_CMD_CPOL; in mtk_spi_prepare_message()
302 reg_val &= ~SPI_CMD_TXMSBF; in mtk_spi_prepare_message()
303 reg_val &= ~SPI_CMD_RXMSBF; in mtk_spi_prepare_message()
305 reg_val |= SPI_CMD_TXMSBF; in mtk_spi_prepare_message()
306 reg_val |= SPI_CMD_RXMSBF; in mtk_spi_prepare_message()
311 reg_val &= ~SPI_CMD_TX_ENDIAN; in mtk_spi_prepare_message()
312 reg_val &= ~SPI_CMD_RX_ENDIAN; in mtk_spi_prepare_message()
314 reg_val |= SPI_CMD_TX_ENDIAN; in mtk_spi_prepare_message()
315 reg_val |= SPI_CMD_RX_ENDIAN; in mtk_spi_prepare_message()
321 reg_val |= SPI_CMD_CS_POL; in mtk_spi_prepare_message()
323 reg_val &= ~SPI_CMD_CS_POL; in mtk_spi_prepare_message()
326 reg_val |= SPI_CMD_SAMPLE_SEL; in mtk_spi_prepare_message()
328 reg_val &= ~SPI_CMD_SAMPLE_SEL; in mtk_spi_prepare_message()
332 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE; in mtk_spi_prepare_message()
335 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); in mtk_spi_prepare_message()
338 reg_val &= ~SPI_CMD_DEASSERT; in mtk_spi_prepare_message()
340 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_prepare_message()
348 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_prepare_message()
349 reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; in mtk_spi_prepare_message()
350 reg_val |= ((chip_config->tick_delay & 0x7) in mtk_spi_prepare_message()
352 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_prepare_message()
361 u32 reg_val; in mtk_spi_set_cs() local
367 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_set_cs()
369 reg_val |= SPI_CMD_PAUSE_EN; in mtk_spi_set_cs()
370 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_set_cs()
372 reg_val &= ~SPI_CMD_PAUSE_EN; in mtk_spi_set_cs()
373 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_set_cs()
382 u32 div, sck_time, reg_val; in mtk_spi_prepare_transfer() local
393 reg_val = readl(mdata->base + SPI_CFG2_REG); in mtk_spi_prepare_transfer()
394 reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET); in mtk_spi_prepare_transfer()
395 reg_val |= (((sck_time - 1) & 0xffff) in mtk_spi_prepare_transfer()
397 reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET); in mtk_spi_prepare_transfer()
398 reg_val |= (((sck_time - 1) & 0xffff) in mtk_spi_prepare_transfer()
400 writel(reg_val, mdata->base + SPI_CFG2_REG); in mtk_spi_prepare_transfer()
402 reg_val = readl(mdata->base + SPI_CFG0_REG); in mtk_spi_prepare_transfer()
403 reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET); in mtk_spi_prepare_transfer()
404 reg_val |= (((sck_time - 1) & 0xff) in mtk_spi_prepare_transfer()
406 reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET); in mtk_spi_prepare_transfer()
407 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); in mtk_spi_prepare_transfer()
408 writel(reg_val, mdata->base + SPI_CFG0_REG); in mtk_spi_prepare_transfer()
414 u32 packet_size, packet_loop, reg_val; in mtk_spi_setup_packet() local
420 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_setup_packet()
421 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK); in mtk_spi_setup_packet()
422 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; in mtk_spi_setup_packet()
423 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; in mtk_spi_setup_packet()
424 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_setup_packet()
511 u32 reg_val; in mtk_spi_fifo_transfer() local
525 reg_val = 0; in mtk_spi_fifo_transfer()
526 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder); in mtk_spi_fifo_transfer()
527 writel(reg_val, mdata->base + SPI_TX_DATA_REG); in mtk_spi_fifo_transfer()
616 u32 cmd, reg_val, cnt, remainder, len; in mtk_spi_interrupt() local
621 reg_val = readl(mdata->base + SPI_STATUS0_REG); in mtk_spi_interrupt()
622 if (reg_val & MTK_SPI_PAUSE_INT_STATUS) in mtk_spi_interrupt()
634 reg_val = readl(mdata->base + SPI_RX_DATA_REG); in mtk_spi_interrupt()
638 ®_val, in mtk_spi_interrupt()
659 reg_val = 0; in mtk_spi_interrupt()
660 memcpy(®_val, in mtk_spi_interrupt()
663 writel(reg_val, mdata->base + SPI_TX_DATA_REG); in mtk_spi_interrupt()