Lines Matching refs:ss
84 static void spi_sh_write(struct spi_sh_data *ss, unsigned long data, in spi_sh_write() argument
87 if (ss->width == 8) in spi_sh_write()
88 iowrite8(data, ss->addr + (offset >> 2)); in spi_sh_write()
89 else if (ss->width == 32) in spi_sh_write()
90 iowrite32(data, ss->addr + offset); in spi_sh_write()
93 static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset) in spi_sh_read() argument
95 if (ss->width == 8) in spi_sh_read()
96 return ioread8(ss->addr + (offset >> 2)); in spi_sh_read()
97 else if (ss->width == 32) in spi_sh_read()
98 return ioread32(ss->addr + offset); in spi_sh_read()
103 static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val, in spi_sh_set_bit() argument
108 tmp = spi_sh_read(ss, offset); in spi_sh_set_bit()
110 spi_sh_write(ss, tmp, offset); in spi_sh_set_bit()
113 static void spi_sh_clear_bit(struct spi_sh_data *ss, unsigned long val, in spi_sh_clear_bit() argument
118 tmp = spi_sh_read(ss, offset); in spi_sh_clear_bit()
120 spi_sh_write(ss, tmp, offset); in spi_sh_clear_bit()
123 static void clear_fifo(struct spi_sh_data *ss) in clear_fifo() argument
125 spi_sh_set_bit(ss, SPI_SH_RSTF, SPI_SH_CR2); in clear_fifo()
126 spi_sh_clear_bit(ss, SPI_SH_RSTF, SPI_SH_CR2); in clear_fifo()
129 static int spi_sh_wait_receive_buffer(struct spi_sh_data *ss) in spi_sh_wait_receive_buffer() argument
133 while (spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) { in spi_sh_wait_receive_buffer()
141 static int spi_sh_wait_write_buffer_empty(struct spi_sh_data *ss) in spi_sh_wait_write_buffer_empty() argument
145 while (!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBE)) { in spi_sh_wait_write_buffer_empty()
153 static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg, in spi_sh_send() argument
163 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1); in spi_sh_send()
169 !(spi_sh_read(ss, SPI_SH_CR4) & in spi_sh_send()
171 !(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBF); in spi_sh_send()
173 spi_sh_write(ss, (unsigned long)data[i], SPI_SH_TBR); in spi_sh_send()
175 if (spi_sh_read(ss, SPI_SH_CR4) & SPI_SH_WPABRT) { in spi_sh_send()
177 spi_sh_set_bit(ss, SPI_SH_WPABRT, SPI_SH_CR4); in spi_sh_send()
188 ss->cr1 &= ~SPI_SH_TBE; in spi_sh_send()
189 spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4); in spi_sh_send()
190 ret = wait_event_interruptible_timeout(ss->wait, in spi_sh_send()
191 ss->cr1 & SPI_SH_TBE, in spi_sh_send()
193 if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) { in spi_sh_send()
201 spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1); in spi_sh_send()
202 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1); in spi_sh_send()
204 ss->cr1 &= ~SPI_SH_TBE; in spi_sh_send()
205 spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4); in spi_sh_send()
206 ret = wait_event_interruptible_timeout(ss->wait, in spi_sh_send()
207 ss->cr1 & SPI_SH_TBE, in spi_sh_send()
209 if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) { in spi_sh_send()
218 static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg, in spi_sh_receive() argument
228 spi_sh_write(ss, SPI_SH_MAX_BYTE, SPI_SH_CR3); in spi_sh_receive()
230 spi_sh_write(ss, t->len, SPI_SH_CR3); in spi_sh_receive()
232 spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1); in spi_sh_receive()
233 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1); in spi_sh_receive()
235 spi_sh_wait_write_buffer_empty(ss); in spi_sh_receive()
240 ss->cr1 &= ~SPI_SH_RBF; in spi_sh_receive()
241 spi_sh_set_bit(ss, SPI_SH_RBF, SPI_SH_CR4); in spi_sh_receive()
242 ret = wait_event_interruptible_timeout(ss->wait, in spi_sh_receive()
243 ss->cr1 & SPI_SH_RBF, in spi_sh_receive()
246 spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) { in spi_sh_receive()
254 if (spi_sh_wait_receive_buffer(ss)) in spi_sh_receive()
256 data[i] = (unsigned char)spi_sh_read(ss, SPI_SH_RBR); in spi_sh_receive()
265 clear_fifo(ss); in spi_sh_receive()
266 spi_sh_write(ss, 1, SPI_SH_CR3); in spi_sh_receive()
268 spi_sh_write(ss, 0, SPI_SH_CR3); in spi_sh_receive()
276 struct spi_sh_data *ss = container_of(work, struct spi_sh_data, ws); in spi_sh_work() local
284 spin_lock_irqsave(&ss->lock, flags); in spi_sh_work()
285 while (!list_empty(&ss->queue)) { in spi_sh_work()
286 mesg = list_entry(ss->queue.next, struct spi_message, queue); in spi_sh_work()
289 spin_unlock_irqrestore(&ss->lock, flags); in spi_sh_work()
297 ret = spi_sh_send(ss, mesg, t); in spi_sh_work()
302 ret = spi_sh_receive(ss, mesg, t); in spi_sh_work()
308 spin_lock_irqsave(&ss->lock, flags); in spi_sh_work()
315 clear_fifo(ss); in spi_sh_work()
316 spi_sh_set_bit(ss, SPI_SH_SSD, SPI_SH_CR1); in spi_sh_work()
319 spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD, in spi_sh_work()
322 clear_fifo(ss); in spi_sh_work()
324 spin_unlock_irqrestore(&ss->lock, flags); in spi_sh_work()
333 spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD, in spi_sh_work()
335 clear_fifo(ss); in spi_sh_work()
341 struct spi_sh_data *ss = spi_master_get_devdata(spi->master); in spi_sh_setup() local
345 spi_sh_write(ss, 0xfe, SPI_SH_CR1); /* SPI sycle stop */ in spi_sh_setup()
346 spi_sh_write(ss, 0x00, SPI_SH_CR1); /* CR1 init */ in spi_sh_setup()
347 spi_sh_write(ss, 0x00, SPI_SH_CR3); /* CR3 init */ in spi_sh_setup()
349 clear_fifo(ss); in spi_sh_setup()
352 spi_sh_write(ss, spi_sh_read(ss, SPI_SH_CR2) | 0x07, SPI_SH_CR2); in spi_sh_setup()
360 struct spi_sh_data *ss = spi_master_get_devdata(spi->master); in spi_sh_transfer() local
366 spin_lock_irqsave(&ss->lock, flags); in spi_sh_transfer()
371 spi_sh_clear_bit(ss, SPI_SH_SSA, SPI_SH_CR1); in spi_sh_transfer()
373 list_add_tail(&mesg->queue, &ss->queue); in spi_sh_transfer()
374 schedule_work(&ss->ws); in spi_sh_transfer()
376 spin_unlock_irqrestore(&ss->lock, flags); in spi_sh_transfer()
383 struct spi_sh_data *ss = spi_master_get_devdata(spi->master); in spi_sh_cleanup() local
387 spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD, in spi_sh_cleanup()
393 struct spi_sh_data *ss = (struct spi_sh_data *)_ss; in spi_sh_irq() local
396 cr1 = spi_sh_read(ss, SPI_SH_CR1); in spi_sh_irq()
398 ss->cr1 |= SPI_SH_TBE; in spi_sh_irq()
400 ss->cr1 |= SPI_SH_TBF; in spi_sh_irq()
402 ss->cr1 |= SPI_SH_RBE; in spi_sh_irq()
404 ss->cr1 |= SPI_SH_RBF; in spi_sh_irq()
406 if (ss->cr1) { in spi_sh_irq()
407 spi_sh_clear_bit(ss, ss->cr1, SPI_SH_CR4); in spi_sh_irq()
408 wake_up(&ss->wait); in spi_sh_irq()
416 struct spi_sh_data *ss = platform_get_drvdata(pdev); in spi_sh_remove() local
418 spi_unregister_master(ss->master); in spi_sh_remove()
419 flush_work(&ss->ws); in spi_sh_remove()
420 free_irq(ss->irq, ss); in spi_sh_remove()
429 struct spi_sh_data *ss; in spi_sh_probe() local
449 ss = spi_master_get_devdata(master); in spi_sh_probe()
450 platform_set_drvdata(pdev, ss); in spi_sh_probe()
454 ss->width = 8; in spi_sh_probe()
457 ss->width = 32; in spi_sh_probe()
463 ss->irq = irq; in spi_sh_probe()
464 ss->master = master; in spi_sh_probe()
465 ss->addr = devm_ioremap(&pdev->dev, res->start, resource_size(res)); in spi_sh_probe()
466 if (ss->addr == NULL) { in spi_sh_probe()
470 INIT_LIST_HEAD(&ss->queue); in spi_sh_probe()
471 spin_lock_init(&ss->lock); in spi_sh_probe()
472 INIT_WORK(&ss->ws, spi_sh_work); in spi_sh_probe()
473 init_waitqueue_head(&ss->wait); in spi_sh_probe()
475 ret = request_irq(irq, spi_sh_irq, 0, "spi_sh", ss); in spi_sh_probe()
496 free_irq(irq, ss); in spi_sh_probe()