Lines Matching refs:spi
99 static void sifive_spi_write(struct sifive_spi *spi, int offset, u32 value) in sifive_spi_write() argument
101 iowrite32(value, spi->regs + offset); in sifive_spi_write()
104 static u32 sifive_spi_read(struct sifive_spi *spi, int offset) in sifive_spi_read() argument
106 return ioread32(spi->regs + offset); in sifive_spi_read()
109 static void sifive_spi_init(struct sifive_spi *spi) in sifive_spi_init() argument
112 sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0); in sifive_spi_init()
115 sifive_spi_write(spi, SIFIVE_SPI_REG_TXMARK, 1); in sifive_spi_init()
116 sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK, 0); in sifive_spi_init()
119 sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY0, in sifive_spi_init()
122 sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY1, in sifive_spi_init()
127 sifive_spi_write(spi, SIFIVE_SPI_REG_FCTRL, 0); in sifive_spi_init()
133 struct sifive_spi *spi = spi_master_get_devdata(master); in sifive_spi_prepare_message() local
134 struct spi_device *device = msg->spi; in sifive_spi_prepare_message()
138 spi->cs_inactive &= ~BIT(device->chip_select); in sifive_spi_prepare_message()
140 spi->cs_inactive |= BIT(device->chip_select); in sifive_spi_prepare_message()
141 sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive); in sifive_spi_prepare_message()
144 sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, device->chip_select); in sifive_spi_prepare_message()
147 sifive_spi_write(spi, SIFIVE_SPI_REG_SCKMODE, in sifive_spi_prepare_message()
155 struct sifive_spi *spi = spi_master_get_devdata(device->master); in sifive_spi_set_cs() local
161 sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE, is_high ? in sifive_spi_set_cs()
167 sifive_spi_prep_transfer(struct sifive_spi *spi, struct spi_device *device, in sifive_spi_prep_transfer() argument
174 cr = DIV_ROUND_UP(clk_get_rate(spi->clk) >> 1, t->speed_hz) - 1; in sifive_spi_prep_transfer()
176 sifive_spi_write(spi, SIFIVE_SPI_REG_SCKDIV, cr); in sifive_spi_prep_transfer()
197 sifive_spi_write(spi, SIFIVE_SPI_REG_FMT, cr); in sifive_spi_prep_transfer()
205 return 1600000 * spi->fifo_depth <= t->speed_hz * mode; in sifive_spi_prep_transfer()
210 struct sifive_spi *spi = dev_id; in sifive_spi_irq() local
211 u32 ip = sifive_spi_read(spi, SIFIVE_SPI_REG_IP); in sifive_spi_irq()
215 sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0); in sifive_spi_irq()
216 complete(&spi->done); in sifive_spi_irq()
223 static void sifive_spi_wait(struct sifive_spi *spi, u32 bit, int poll) in sifive_spi_wait() argument
229 cr = sifive_spi_read(spi, SIFIVE_SPI_REG_IP); in sifive_spi_wait()
232 reinit_completion(&spi->done); in sifive_spi_wait()
233 sifive_spi_write(spi, SIFIVE_SPI_REG_IE, bit); in sifive_spi_wait()
234 wait_for_completion(&spi->done); in sifive_spi_wait()
238 static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr) in sifive_spi_tx() argument
240 WARN_ON_ONCE((sifive_spi_read(spi, SIFIVE_SPI_REG_TXDATA) in sifive_spi_tx()
242 sifive_spi_write(spi, SIFIVE_SPI_REG_TXDATA, in sifive_spi_tx()
246 static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr) in sifive_spi_rx() argument
248 u32 data = sifive_spi_read(spi, SIFIVE_SPI_REG_RXDATA); in sifive_spi_rx()
258 struct sifive_spi *spi = spi_master_get_devdata(master); in sifive_spi_transfer_one() local
259 int poll = sifive_spi_prep_transfer(spi, device, t); in sifive_spi_transfer_one()
265 unsigned int n_words = min(remaining_words, spi->fifo_depth); in sifive_spi_transfer_one()
270 sifive_spi_tx(spi, tx_ptr++); in sifive_spi_transfer_one()
274 sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK, in sifive_spi_transfer_one()
276 sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM, poll); in sifive_spi_transfer_one()
280 sifive_spi_rx(spi, rx_ptr++); in sifive_spi_transfer_one()
283 sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM, poll); in sifive_spi_transfer_one()
294 struct sifive_spi *spi; in sifive_spi_probe() local
305 spi = spi_master_get_devdata(master); in sifive_spi_probe()
306 init_completion(&spi->done); in sifive_spi_probe()
309 spi->regs = devm_platform_ioremap_resource(pdev, 0); in sifive_spi_probe()
310 if (IS_ERR(spi->regs)) { in sifive_spi_probe()
311 ret = PTR_ERR(spi->regs); in sifive_spi_probe()
315 spi->clk = devm_clk_get(&pdev->dev, NULL); in sifive_spi_probe()
316 if (IS_ERR(spi->clk)) { in sifive_spi_probe()
318 ret = PTR_ERR(spi->clk); in sifive_spi_probe()
331 &spi->fifo_depth); in sifive_spi_probe()
333 spi->fifo_depth = SIFIVE_SPI_DEFAULT_DEPTH; in sifive_spi_probe()
346 ret = clk_prepare_enable(spi->clk); in sifive_spi_probe()
353 spi->cs_inactive = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF); in sifive_spi_probe()
354 sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, 0xffffffffU); in sifive_spi_probe()
355 cs_bits = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF); in sifive_spi_probe()
356 sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive); in sifive_spi_probe()
389 sifive_spi_init(spi); in sifive_spi_probe()
393 dev_name(&pdev->dev), spi); in sifive_spi_probe()
411 clk_disable_unprepare(spi->clk); in sifive_spi_probe()
421 struct sifive_spi *spi = spi_master_get_devdata(master); in sifive_spi_remove() local
424 sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0); in sifive_spi_remove()
425 clk_disable_unprepare(spi->clk); in sifive_spi_remove()