Lines Matching refs:readb
65 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_tx()
76 cr = readb(uap->port.membase + UART010_CR); in pl010_start_tx()
87 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_rx()
97 cr = readb(uap->port.membase + UART010_CR); in pl010_disable_ms()
108 cr = readb(uap->port.membase + UART010_CR); in pl010_enable_ms()
117 status = readb(uap->port.membase + UART01x_FR); in pl010_rx_chars()
119 ch = readb(uap->port.membase + UART01x_DR); in pl010_rx_chars()
128 rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX; in pl010_rx_chars()
160 status = readb(uap->port.membase + UART01x_FR); in pl010_rx_chars()
203 status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; in pl010_modem_status()
231 status = readb(uap->port.membase + UART010_IIR); in pl010_int()
244 status = readb(uap->port.membase + UART010_IIR); in pl010_int()
259 unsigned int status = readb(uap->port.membase + UART01x_FR); in pl010_tx_empty()
270 status = readb(uap->port.membase + UART01x_FR); in pl010_get_mctrl()
298 lcr_h = readb(uap->port.membase + UART010_LCRH); in pl010_break_ctl()
332 uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; in pl010_startup()
364 writel(readb(uap->port.membase + UART010_LCRH) & in pl010_shutdown()
450 old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE; in pl010_set_termios()
569 status = readb(uap->port.membase + UART01x_FR); in pl010_console_putchar()
586 old_cr = readb(uap->port.membase + UART010_CR); in pl010_console_write()
596 status = readb(uap->port.membase + UART01x_FR); in pl010_console_write()
608 if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) { in pl010_console_get_options()
610 lcr_h = readb(uap->port.membase + UART010_LCRH); in pl010_console_get_options()
625 quot = readb(uap->port.membase + UART010_LCRL) | in pl010_console_get_options()
626 readb(uap->port.membase + UART010_LCRM) << 8; in pl010_console_get_options()