Lines Matching refs:sport
276 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) in imx_uart_writel() argument
280 sport->ucr1 = val; in imx_uart_writel()
283 sport->ucr2 = val; in imx_uart_writel()
286 sport->ucr3 = val; in imx_uart_writel()
289 sport->ucr4 = val; in imx_uart_writel()
292 sport->ufcr = val; in imx_uart_writel()
297 writel(val, sport->port.membase + offset); in imx_uart_writel()
300 static u32 imx_uart_readl(struct imx_port *sport, u32 offset) in imx_uart_readl() argument
304 return sport->ucr1; in imx_uart_readl()
313 if (!(sport->ucr2 & UCR2_SRST)) in imx_uart_readl()
314 sport->ucr2 = readl(sport->port.membase + offset); in imx_uart_readl()
315 return sport->ucr2; in imx_uart_readl()
318 return sport->ucr3; in imx_uart_readl()
321 return sport->ucr4; in imx_uart_readl()
324 return sport->ufcr; in imx_uart_readl()
327 return readl(sport->port.membase + offset); in imx_uart_readl()
331 static inline unsigned imx_uart_uts_reg(struct imx_port *sport) in imx_uart_uts_reg() argument
333 return sport->devdata->uts_reg; in imx_uart_uts_reg()
336 static inline int imx_uart_is_imx1(struct imx_port *sport) in imx_uart_is_imx1() argument
338 return sport->devdata->devtype == IMX1_UART; in imx_uart_is_imx1()
341 static inline int imx_uart_is_imx21(struct imx_port *sport) in imx_uart_is_imx21() argument
343 return sport->devdata->devtype == IMX21_UART; in imx_uart_is_imx21()
346 static inline int imx_uart_is_imx53(struct imx_port *sport) in imx_uart_is_imx53() argument
348 return sport->devdata->devtype == IMX53_UART; in imx_uart_is_imx53()
351 static inline int imx_uart_is_imx6q(struct imx_port *sport) in imx_uart_is_imx6q() argument
353 return sport->devdata->devtype == IMX6Q_UART; in imx_uart_is_imx6q()
359 static void imx_uart_ucrs_save(struct imx_port *sport, in imx_uart_ucrs_save() argument
363 ucr->ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_ucrs_save()
364 ucr->ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_ucrs_save()
365 ucr->ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_ucrs_save()
368 static void imx_uart_ucrs_restore(struct imx_port *sport, in imx_uart_ucrs_restore() argument
372 imx_uart_writel(sport, ucr->ucr1, UCR1); in imx_uart_ucrs_restore()
373 imx_uart_writel(sport, ucr->ucr2, UCR2); in imx_uart_ucrs_restore()
374 imx_uart_writel(sport, ucr->ucr3, UCR3); in imx_uart_ucrs_restore()
379 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) in imx_uart_rts_active() argument
383 sport->port.mctrl |= TIOCM_RTS; in imx_uart_rts_active()
384 mctrl_gpio_set(sport->gpios, sport->port.mctrl); in imx_uart_rts_active()
388 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) in imx_uart_rts_inactive() argument
393 sport->port.mctrl &= ~TIOCM_RTS; in imx_uart_rts_inactive()
394 mctrl_gpio_set(sport->gpios, sport->port.mctrl); in imx_uart_rts_inactive()
405 struct imx_port *sport = (struct imx_port *)port; in imx_uart_start_rx() local
408 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_start_rx()
409 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_start_rx()
413 if (sport->dma_is_enabled) { in imx_uart_start_rx()
421 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_start_rx()
422 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_start_rx()
428 struct imx_port *sport = (struct imx_port *)port; in imx_uart_stop_tx() local
431 if (sport->tx_state == OFF) in imx_uart_stop_tx()
438 if (sport->dma_is_txing) in imx_uart_stop_tx()
441 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_stop_tx()
442 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); in imx_uart_stop_tx()
444 usr2 = imx_uart_readl(sport, USR2); in imx_uart_stop_tx()
450 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_stop_tx()
452 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_stop_tx()
456 if (sport->tx_state == SEND) { in imx_uart_stop_tx()
457 sport->tx_state = WAIT_AFTER_SEND; in imx_uart_stop_tx()
458 start_hrtimer_ms(&sport->trigger_stop_tx, in imx_uart_stop_tx()
463 if (sport->tx_state == WAIT_AFTER_RTS || in imx_uart_stop_tx()
464 sport->tx_state == WAIT_AFTER_SEND) { in imx_uart_stop_tx()
467 hrtimer_try_to_cancel(&sport->trigger_start_tx); in imx_uart_stop_tx()
469 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_stop_tx()
471 imx_uart_rts_active(sport, &ucr2); in imx_uart_stop_tx()
473 imx_uart_rts_inactive(sport, &ucr2); in imx_uart_stop_tx()
474 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_stop_tx()
478 sport->tx_state = OFF; in imx_uart_stop_tx()
481 sport->tx_state = OFF; in imx_uart_stop_tx()
488 struct imx_port *sport = (struct imx_port *)port; in imx_uart_stop_rx() local
491 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_stop_rx()
492 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_stop_rx()
494 if (sport->dma_is_enabled) { in imx_uart_stop_rx()
500 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_stop_rx()
503 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_stop_rx()
509 struct imx_port *sport = (struct imx_port *)port; in imx_uart_enable_ms() local
511 mod_timer(&sport->timer, jiffies); in imx_uart_enable_ms()
513 mctrl_gpio_enable_ms(sport->gpios); in imx_uart_enable_ms()
516 static void imx_uart_dma_tx(struct imx_port *sport);
519 static inline void imx_uart_transmit_buffer(struct imx_port *sport) in imx_uart_transmit_buffer() argument
521 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_transmit_buffer()
523 if (sport->port.x_char) { in imx_uart_transmit_buffer()
525 imx_uart_writel(sport, sport->port.x_char, URTX0); in imx_uart_transmit_buffer()
526 sport->port.icount.tx++; in imx_uart_transmit_buffer()
527 sport->port.x_char = 0; in imx_uart_transmit_buffer()
531 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { in imx_uart_transmit_buffer()
532 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
536 if (sport->dma_is_enabled) { in imx_uart_transmit_buffer()
542 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_transmit_buffer()
544 if (sport->dma_is_txing) { in imx_uart_transmit_buffer()
546 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_transmit_buffer()
548 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_transmit_buffer()
549 imx_uart_dma_tx(sport); in imx_uart_transmit_buffer()
556 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { in imx_uart_transmit_buffer()
559 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); in imx_uart_transmit_buffer()
561 sport->port.icount.tx++; in imx_uart_transmit_buffer()
565 uart_write_wakeup(&sport->port); in imx_uart_transmit_buffer()
568 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
573 struct imx_port *sport = data; in imx_uart_dma_tx_callback() local
574 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_dma_tx_callback()
575 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx_callback()
579 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
581 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx_callback()
583 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_dma_tx_callback()
585 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_dma_tx_callback()
588 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); in imx_uart_dma_tx_callback()
589 sport->port.icount.tx += sport->tx_bytes; in imx_uart_dma_tx_callback()
591 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); in imx_uart_dma_tx_callback()
593 sport->dma_is_txing = 0; in imx_uart_dma_tx_callback()
596 uart_write_wakeup(&sport->port); in imx_uart_dma_tx_callback()
598 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) in imx_uart_dma_tx_callback()
599 imx_uart_dma_tx(sport); in imx_uart_dma_tx_callback()
600 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { in imx_uart_dma_tx_callback()
601 u32 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_dma_tx_callback()
603 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_dma_tx_callback()
606 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
610 static void imx_uart_dma_tx(struct imx_port *sport) in imx_uart_dma_tx() argument
612 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx()
613 struct scatterlist *sgl = sport->tx_sgl; in imx_uart_dma_tx()
615 struct dma_chan *chan = sport->dma_chan_tx; in imx_uart_dma_tx()
616 struct device *dev = sport->port.dev; in imx_uart_dma_tx()
620 if (sport->dma_is_txing) in imx_uart_dma_tx()
623 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_dma_tx()
625 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_dma_tx()
627 sport->tx_bytes = uart_circ_chars_pending(xmit); in imx_uart_dma_tx()
630 sport->dma_tx_nents = 1; in imx_uart_dma_tx()
631 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); in imx_uart_dma_tx()
633 sport->dma_tx_nents = 2; in imx_uart_dma_tx()
640 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx()
648 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, in imx_uart_dma_tx()
654 desc->callback_param = sport; in imx_uart_dma_tx()
659 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_dma_tx()
661 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_dma_tx()
664 sport->dma_is_txing = 1; in imx_uart_dma_tx()
673 struct imx_port *sport = (struct imx_port *)port; in imx_uart_start_tx() local
676 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) in imx_uart_start_tx()
686 if (sport->tx_state == OFF) { in imx_uart_start_tx()
687 u32 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_start_tx()
689 imx_uart_rts_active(sport, &ucr2); in imx_uart_start_tx()
691 imx_uart_rts_inactive(sport, &ucr2); in imx_uart_start_tx()
692 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_start_tx()
697 sport->tx_state = WAIT_AFTER_RTS; in imx_uart_start_tx()
698 start_hrtimer_ms(&sport->trigger_start_tx, in imx_uart_start_tx()
703 if (sport->tx_state == WAIT_AFTER_SEND in imx_uart_start_tx()
704 || sport->tx_state == WAIT_AFTER_RTS) { in imx_uart_start_tx()
706 hrtimer_try_to_cancel(&sport->trigger_stop_tx); in imx_uart_start_tx()
713 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
714 u32 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_start_tx()
716 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_start_tx()
719 sport->tx_state = SEND; in imx_uart_start_tx()
722 sport->tx_state = SEND; in imx_uart_start_tx()
725 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
726 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_start_tx()
727 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); in imx_uart_start_tx()
730 if (sport->dma_is_enabled) { in imx_uart_start_tx()
731 if (sport->port.x_char) { in imx_uart_start_tx()
734 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_start_tx()
737 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_start_tx()
743 imx_uart_dma_tx(sport); in imx_uart_start_tx()
750 struct imx_port *sport = dev_id; in __imx_uart_rtsint() local
753 imx_uart_writel(sport, USR1_RTSD, USR1); in __imx_uart_rtsint()
754 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; in __imx_uart_rtsint()
755 uart_handle_cts_change(&sport->port, !!usr1); in __imx_uart_rtsint()
756 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in __imx_uart_rtsint()
763 struct imx_port *sport = dev_id; in imx_uart_rtsint() local
766 spin_lock(&sport->port.lock); in imx_uart_rtsint()
770 spin_unlock(&sport->port.lock); in imx_uart_rtsint()
777 struct imx_port *sport = dev_id; in imx_uart_txint() local
779 spin_lock(&sport->port.lock); in imx_uart_txint()
780 imx_uart_transmit_buffer(sport); in imx_uart_txint()
781 spin_unlock(&sport->port.lock); in imx_uart_txint()
787 struct imx_port *sport = dev_id; in __imx_uart_rxint() local
789 struct tty_port *port = &sport->port.state->port; in __imx_uart_rxint()
791 while (imx_uart_readl(sport, USR2) & USR2_RDR) { in __imx_uart_rxint()
795 sport->port.icount.rx++; in __imx_uart_rxint()
797 rx = imx_uart_readl(sport, URXD0); in __imx_uart_rxint()
799 usr2 = imx_uart_readl(sport, USR2); in __imx_uart_rxint()
801 imx_uart_writel(sport, USR2_BRCD, USR2); in __imx_uart_rxint()
802 if (uart_handle_break(&sport->port)) in __imx_uart_rxint()
806 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) in __imx_uart_rxint()
811 sport->port.icount.brk++; in __imx_uart_rxint()
813 sport->port.icount.parity++; in __imx_uart_rxint()
815 sport->port.icount.frame++; in __imx_uart_rxint()
817 sport->port.icount.overrun++; in __imx_uart_rxint()
819 if (rx & sport->port.ignore_status_mask) { in __imx_uart_rxint()
825 rx &= (sport->port.read_status_mask | 0xFF); in __imx_uart_rxint()
836 sport->port.sysrq = 0; in __imx_uart_rxint()
839 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) in __imx_uart_rxint()
843 sport->port.icount.buf_overrun++; in __imx_uart_rxint()
854 struct imx_port *sport = dev_id; in imx_uart_rxint() local
857 spin_lock(&sport->port.lock); in imx_uart_rxint()
861 spin_unlock(&sport->port.lock); in imx_uart_rxint()
866 static void imx_uart_clear_rx_errors(struct imx_port *sport);
871 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) in imx_uart_get_hwmctrl() argument
874 unsigned usr1 = imx_uart_readl(sport, USR1); in imx_uart_get_hwmctrl()
875 unsigned usr2 = imx_uart_readl(sport, USR2); in imx_uart_get_hwmctrl()
884 if (sport->dte_mode) in imx_uart_get_hwmctrl()
885 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) in imx_uart_get_hwmctrl()
894 static void imx_uart_mctrl_check(struct imx_port *sport) in imx_uart_mctrl_check() argument
898 status = imx_uart_get_hwmctrl(sport); in imx_uart_mctrl_check()
899 changed = status ^ sport->old_status; in imx_uart_mctrl_check()
904 sport->old_status = status; in imx_uart_mctrl_check()
907 sport->port.icount.rng++; in imx_uart_mctrl_check()
909 sport->port.icount.dsr++; in imx_uart_mctrl_check()
911 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); in imx_uart_mctrl_check()
913 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); in imx_uart_mctrl_check()
915 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in imx_uart_mctrl_check()
920 struct imx_port *sport = dev_id; in imx_uart_int() local
924 spin_lock(&sport->port.lock); in imx_uart_int()
926 usr1 = imx_uart_readl(sport, USR1); in imx_uart_int()
927 usr2 = imx_uart_readl(sport, USR2); in imx_uart_int()
928 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_int()
929 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_int()
930 ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_int()
931 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_int()
959 imx_uart_writel(sport, USR1_AGTIM, USR1); in imx_uart_int()
966 imx_uart_transmit_buffer(sport); in imx_uart_int()
971 imx_uart_writel(sport, USR1_DTRD, USR1); in imx_uart_int()
973 imx_uart_mctrl_check(sport); in imx_uart_int()
984 imx_uart_writel(sport, USR1_AWAKE, USR1); in imx_uart_int()
989 sport->port.icount.overrun++; in imx_uart_int()
990 imx_uart_writel(sport, USR2_ORE, USR2); in imx_uart_int()
994 spin_unlock(&sport->port.lock); in imx_uart_int()
1004 struct imx_port *sport = (struct imx_port *)port; in imx_uart_tx_empty() local
1007 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; in imx_uart_tx_empty()
1010 if (sport->dma_is_txing) in imx_uart_tx_empty()
1019 struct imx_port *sport = (struct imx_port *)port; in imx_uart_get_mctrl() local
1020 unsigned int ret = imx_uart_get_hwmctrl(sport); in imx_uart_get_mctrl()
1022 mctrl_gpio_get(sport->gpios, &ret); in imx_uart_get_mctrl()
1030 struct imx_port *sport = (struct imx_port *)port; in imx_uart_set_mctrl() local
1040 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_set_mctrl()
1052 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_set_mctrl()
1055 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; in imx_uart_set_mctrl()
1058 imx_uart_writel(sport, ucr3, UCR3); in imx_uart_set_mctrl()
1060 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; in imx_uart_set_mctrl()
1063 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); in imx_uart_set_mctrl()
1065 mctrl_gpio_set(sport->gpios, mctrl); in imx_uart_set_mctrl()
1073 struct imx_port *sport = (struct imx_port *)port; in imx_uart_break_ctl() local
1077 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_break_ctl()
1079 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; in imx_uart_break_ctl()
1084 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_break_ctl()
1086 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_break_ctl()
1095 struct imx_port *sport = from_timer(sport, t, timer); in imx_uart_timeout() local
1098 if (sport->port.state) { in imx_uart_timeout()
1099 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_timeout()
1100 imx_uart_mctrl_check(sport); in imx_uart_timeout()
1101 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_timeout()
1103 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); in imx_uart_timeout()
1117 struct imx_port *sport = data; in imx_uart_dma_rx_callback() local
1118 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_dma_rx_callback()
1119 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_dma_rx_callback()
1120 struct tty_port *port = &sport->port.state->port; in imx_uart_dma_rx_callback()
1122 struct circ_buf *rx_ring = &sport->rx_ring; in imx_uart_dma_rx_callback()
1128 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); in imx_uart_dma_rx_callback()
1131 imx_uart_clear_rx_errors(sport); in imx_uart_dma_rx_callback()
1135 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { in imx_uart_dma_rx_callback()
1152 bd_size = sg_dma_len(sgl) / sport->rx_periods; in imx_uart_dma_rx_callback()
1162 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1166 sport->rx_buf + rx_ring->tail, r_bytes); in imx_uart_dma_rx_callback()
1169 dma_sync_sg_for_device(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1173 sport->port.icount.buf_overrun++; in imx_uart_dma_rx_callback()
1175 sport->port.icount.rx += w_bytes; in imx_uart_dma_rx_callback()
1184 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); in imx_uart_dma_rx_callback()
1188 static int imx_uart_start_rx_dma(struct imx_port *sport) in imx_uart_start_rx_dma() argument
1190 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_start_rx_dma()
1191 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_start_rx_dma()
1192 struct device *dev = sport->port.dev; in imx_uart_start_rx_dma()
1196 sport->rx_ring.head = 0; in imx_uart_start_rx_dma()
1197 sport->rx_ring.tail = 0; in imx_uart_start_rx_dma()
1199 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); in imx_uart_start_rx_dma()
1207 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, in imx_uart_start_rx_dma()
1216 desc->callback_param = sport; in imx_uart_start_rx_dma()
1219 sport->dma_is_rxing = 1; in imx_uart_start_rx_dma()
1220 sport->rx_cookie = dmaengine_submit(desc); in imx_uart_start_rx_dma()
1225 static void imx_uart_clear_rx_errors(struct imx_port *sport) in imx_uart_clear_rx_errors() argument
1227 struct tty_port *port = &sport->port.state->port; in imx_uart_clear_rx_errors()
1230 usr1 = imx_uart_readl(sport, USR1); in imx_uart_clear_rx_errors()
1231 usr2 = imx_uart_readl(sport, USR2); in imx_uart_clear_rx_errors()
1234 sport->port.icount.brk++; in imx_uart_clear_rx_errors()
1235 imx_uart_writel(sport, USR2_BRCD, USR2); in imx_uart_clear_rx_errors()
1236 uart_handle_break(&sport->port); in imx_uart_clear_rx_errors()
1238 sport->port.icount.buf_overrun++; in imx_uart_clear_rx_errors()
1242 sport->port.icount.frame++; in imx_uart_clear_rx_errors()
1243 imx_uart_writel(sport, USR1_FRAMERR, USR1); in imx_uart_clear_rx_errors()
1245 sport->port.icount.parity++; in imx_uart_clear_rx_errors()
1246 imx_uart_writel(sport, USR1_PARITYERR, USR1); in imx_uart_clear_rx_errors()
1251 sport->port.icount.overrun++; in imx_uart_clear_rx_errors()
1252 imx_uart_writel(sport, USR2_ORE, USR2); in imx_uart_clear_rx_errors()
1262 static void imx_uart_setup_ufcr(struct imx_port *sport, in imx_uart_setup_ufcr() argument
1268 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); in imx_uart_setup_ufcr()
1270 imx_uart_writel(sport, val, UFCR); in imx_uart_setup_ufcr()
1273 static void imx_uart_dma_exit(struct imx_port *sport) in imx_uart_dma_exit() argument
1275 if (sport->dma_chan_rx) { in imx_uart_dma_exit()
1276 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_dma_exit()
1277 dma_release_channel(sport->dma_chan_rx); in imx_uart_dma_exit()
1278 sport->dma_chan_rx = NULL; in imx_uart_dma_exit()
1279 sport->rx_cookie = -EINVAL; in imx_uart_dma_exit()
1280 kfree(sport->rx_buf); in imx_uart_dma_exit()
1281 sport->rx_buf = NULL; in imx_uart_dma_exit()
1284 if (sport->dma_chan_tx) { in imx_uart_dma_exit()
1285 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_dma_exit()
1286 dma_release_channel(sport->dma_chan_tx); in imx_uart_dma_exit()
1287 sport->dma_chan_tx = NULL; in imx_uart_dma_exit()
1291 static int imx_uart_dma_init(struct imx_port *sport) in imx_uart_dma_init() argument
1294 struct device *dev = sport->port.dev; in imx_uart_dma_init()
1298 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); in imx_uart_dma_init()
1299 if (!sport->dma_chan_rx) { in imx_uart_dma_init()
1306 slave_config.src_addr = sport->port.mapbase + URXD0; in imx_uart_dma_init()
1310 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); in imx_uart_dma_init()
1316 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; in imx_uart_dma_init()
1317 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL); in imx_uart_dma_init()
1318 if (!sport->rx_buf) { in imx_uart_dma_init()
1322 sport->rx_ring.buf = sport->rx_buf; in imx_uart_dma_init()
1325 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); in imx_uart_dma_init()
1326 if (!sport->dma_chan_tx) { in imx_uart_dma_init()
1333 slave_config.dst_addr = sport->port.mapbase + URTX0; in imx_uart_dma_init()
1336 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); in imx_uart_dma_init()
1344 imx_uart_dma_exit(sport); in imx_uart_dma_init()
1348 static void imx_uart_enable_dma(struct imx_port *sport) in imx_uart_enable_dma() argument
1352 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); in imx_uart_enable_dma()
1355 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_enable_dma()
1357 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_enable_dma()
1359 sport->dma_is_enabled = 1; in imx_uart_enable_dma()
1362 static void imx_uart_disable_dma(struct imx_port *sport) in imx_uart_disable_dma() argument
1367 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_disable_dma()
1369 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_disable_dma()
1371 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); in imx_uart_disable_dma()
1373 sport->dma_is_enabled = 0; in imx_uart_disable_dma()
1381 struct imx_port *sport = (struct imx_port *)port; in imx_uart_startup() local
1387 retval = clk_prepare_enable(sport->clk_per); in imx_uart_startup()
1390 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_startup()
1392 clk_disable_unprepare(sport->clk_per); in imx_uart_startup()
1396 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); in imx_uart_startup()
1401 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_startup()
1407 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); in imx_uart_startup()
1410 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) in imx_uart_startup()
1413 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_startup()
1417 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_startup()
1419 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_startup()
1421 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_startup()
1427 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); in imx_uart_startup()
1428 imx_uart_writel(sport, USR2_ORE, USR2); in imx_uart_startup()
1430 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; in imx_uart_startup()
1432 if (sport->have_rtscts) in imx_uart_startup()
1435 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_startup()
1437 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR); in imx_uart_startup()
1438 if (!sport->dma_is_enabled) in imx_uart_startup()
1440 if (sport->inverted_rx) in imx_uart_startup()
1442 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_startup()
1444 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT; in imx_uart_startup()
1448 if (sport->inverted_tx) in imx_uart_startup()
1451 if (!imx_uart_is_imx1(sport)) { in imx_uart_startup()
1454 if (sport->dte_mode) in imx_uart_startup()
1458 imx_uart_writel(sport, ucr3, UCR3); in imx_uart_startup()
1460 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; in imx_uart_startup()
1462 if (!sport->have_rtscts) in imx_uart_startup()
1468 if (!imx_uart_is_imx1(sport)) in imx_uart_startup()
1470 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_startup()
1475 imx_uart_enable_ms(&sport->port); in imx_uart_startup()
1478 imx_uart_enable_dma(sport); in imx_uart_startup()
1479 imx_uart_start_rx_dma(sport); in imx_uart_startup()
1481 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_startup()
1483 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_startup()
1485 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_startup()
1487 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_startup()
1490 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_startup()
1497 struct imx_port *sport = (struct imx_port *)port; in imx_uart_shutdown() local
1501 if (sport->dma_is_enabled) { in imx_uart_shutdown()
1502 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_shutdown()
1503 if (sport->dma_is_txing) { in imx_uart_shutdown()
1504 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], in imx_uart_shutdown()
1505 sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_shutdown()
1506 sport->dma_is_txing = 0; in imx_uart_shutdown()
1508 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_shutdown()
1509 if (sport->dma_is_rxing) { in imx_uart_shutdown()
1510 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, in imx_uart_shutdown()
1512 sport->dma_is_rxing = 0; in imx_uart_shutdown()
1515 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1518 imx_uart_disable_dma(sport); in imx_uart_shutdown()
1519 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1520 imx_uart_dma_exit(sport); in imx_uart_shutdown()
1523 mctrl_gpio_disable_ms(sport->gpios); in imx_uart_shutdown()
1525 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1526 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_shutdown()
1528 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_shutdown()
1529 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1534 del_timer_sync(&sport->timer); in imx_uart_shutdown()
1540 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1542 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_shutdown()
1544 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_shutdown()
1546 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_shutdown()
1548 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_shutdown()
1550 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1552 clk_disable_unprepare(sport->clk_per); in imx_uart_shutdown()
1553 clk_disable_unprepare(sport->clk_ipg); in imx_uart_shutdown()
1559 struct imx_port *sport = (struct imx_port *)port; in imx_uart_flush_buffer() local
1560 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_flush_buffer()
1564 if (!sport->dma_chan_tx) in imx_uart_flush_buffer()
1567 sport->tx_bytes = 0; in imx_uart_flush_buffer()
1568 dmaengine_terminate_all(sport->dma_chan_tx); in imx_uart_flush_buffer()
1569 if (sport->dma_is_txing) { in imx_uart_flush_buffer()
1572 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, in imx_uart_flush_buffer()
1574 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_flush_buffer()
1576 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_flush_buffer()
1577 sport->dma_is_txing = 0; in imx_uart_flush_buffer()
1591 ubir = imx_uart_readl(sport, UBIR); in imx_uart_flush_buffer()
1592 ubmr = imx_uart_readl(sport, UBMR); in imx_uart_flush_buffer()
1593 uts = imx_uart_readl(sport, IMX21_UTS); in imx_uart_flush_buffer()
1595 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_flush_buffer()
1597 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_flush_buffer()
1599 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_flush_buffer()
1603 imx_uart_writel(sport, ubir, UBIR); in imx_uart_flush_buffer()
1604 imx_uart_writel(sport, ubmr, UBMR); in imx_uart_flush_buffer()
1605 imx_uart_writel(sport, uts, IMX21_UTS); in imx_uart_flush_buffer()
1612 struct imx_port *sport = (struct imx_port *)port; in imx_uart_set_termios() local
1631 del_timer_sync(&sport->timer); in imx_uart_set_termios()
1639 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_set_termios()
1645 old_ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_set_termios()
1652 if (!sport->have_rtscts) in imx_uart_set_termios()
1662 imx_uart_rts_active(sport, &ucr2); in imx_uart_set_termios()
1664 imx_uart_rts_inactive(sport, &ucr2); in imx_uart_set_termios()
1685 sport->port.read_status_mask = 0; in imx_uart_set_termios()
1687 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); in imx_uart_set_termios()
1689 sport->port.read_status_mask |= URXD_BRK; in imx_uart_set_termios()
1694 sport->port.ignore_status_mask = 0; in imx_uart_set_termios()
1696 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; in imx_uart_set_termios()
1698 sport->port.ignore_status_mask |= URXD_BRK; in imx_uart_set_termios()
1704 sport->port.ignore_status_mask |= URXD_OVRRUN; in imx_uart_set_termios()
1708 sport->port.ignore_status_mask |= URXD_DUMMY_READ; in imx_uart_set_termios()
1716 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1718 baud = sport->port.uartclk / (quot * 16); in imx_uart_set_termios()
1720 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1726 rational_best_approximation(16 * div * baud, sport->port.uartclk, in imx_uart_set_termios()
1729 tdiv64 = sport->port.uartclk; in imx_uart_set_termios()
1738 ufcr = imx_uart_readl(sport, UFCR); in imx_uart_set_termios()
1740 imx_uart_writel(sport, ufcr, UFCR); in imx_uart_set_termios()
1751 old_ubir = imx_uart_readl(sport, UBIR); in imx_uart_set_termios()
1752 old_ubmr = imx_uart_readl(sport, UBMR); in imx_uart_set_termios()
1754 imx_uart_writel(sport, num, UBIR); in imx_uart_set_termios()
1755 imx_uart_writel(sport, denom, UBMR); in imx_uart_set_termios()
1758 if (!imx_uart_is_imx1(sport)) in imx_uart_set_termios()
1759 imx_uart_writel(sport, sport->port.uartclk / div / 1000, in imx_uart_set_termios()
1762 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_set_termios()
1764 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) in imx_uart_set_termios()
1765 imx_uart_enable_ms(&sport->port); in imx_uart_set_termios()
1767 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_set_termios()
1772 struct imx_port *sport = (struct imx_port *)port; in imx_uart_type() local
1774 return sport->port.type == PORT_IMX ? "IMX" : NULL; in imx_uart_type()
1782 struct imx_port *sport = (struct imx_port *)port; in imx_uart_config_port() local
1785 sport->port.type = PORT_IMX; in imx_uart_config_port()
1796 struct imx_port *sport = (struct imx_port *)port; in imx_uart_verify_port() local
1801 if (sport->port.irq != ser->irq) in imx_uart_verify_port()
1805 if (sport->port.uartclk / 16 != ser->baud_base) in imx_uart_verify_port()
1807 if (sport->port.mapbase != (unsigned long)ser->iomem_base) in imx_uart_verify_port()
1809 if (sport->port.iobase != ser->port) in imx_uart_verify_port()
1820 struct imx_port *sport = (struct imx_port *)port; in imx_uart_poll_init() local
1825 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_poll_init()
1828 retval = clk_prepare_enable(sport->clk_per); in imx_uart_poll_init()
1830 clk_disable_unprepare(sport->clk_ipg); in imx_uart_poll_init()
1832 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); in imx_uart_poll_init()
1834 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_poll_init()
1843 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_poll_init()
1844 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_poll_init()
1846 if (imx_uart_is_imx1(sport)) in imx_uart_poll_init()
1855 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_poll_init()
1856 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_poll_init()
1859 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); in imx_uart_poll_init()
1860 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); in imx_uart_poll_init()
1862 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_poll_init()
1869 struct imx_port *sport = (struct imx_port *)port; in imx_uart_poll_get_char() local
1870 if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) in imx_uart_poll_get_char()
1873 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; in imx_uart_poll_get_char()
1878 struct imx_port *sport = (struct imx_port *)port; in imx_uart_poll_put_char() local
1883 status = imx_uart_readl(sport, USR1); in imx_uart_poll_put_char()
1887 imx_uart_writel(sport, c, URTX0); in imx_uart_poll_put_char()
1891 status = imx_uart_readl(sport, USR2); in imx_uart_poll_put_char()
1900 struct imx_port *sport = (struct imx_port *)port; in imx_uart_rs485_config() local
1904 if (!sport->have_rtscts && !sport->have_rtsgpio) in imx_uart_rs485_config()
1909 if (sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_rs485_config()
1914 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_rs485_config()
1916 imx_uart_rts_active(sport, &ucr2); in imx_uart_rs485_config()
1918 imx_uart_rts_inactive(sport, &ucr2); in imx_uart_rs485_config()
1919 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_rs485_config()
1960 struct imx_port *sport = (struct imx_port *)port; in imx_uart_console_putchar() local
1962 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) in imx_uart_console_putchar()
1965 imx_uart_writel(sport, ch, URTX0); in imx_uart_console_putchar()
1974 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_write() local
1980 if (sport->port.sysrq) in imx_uart_console_write()
1983 locked = spin_trylock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
1985 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
1990 imx_uart_ucrs_save(sport, &old_ucr); in imx_uart_console_write()
1993 if (imx_uart_is_imx1(sport)) in imx_uart_console_write()
1998 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_console_write()
2000 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); in imx_uart_console_write()
2002 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); in imx_uart_console_write()
2008 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); in imx_uart_console_write()
2010 imx_uart_ucrs_restore(sport, &old_ucr); in imx_uart_console_write()
2013 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_console_write()
2021 imx_uart_console_get_options(struct imx_port *sport, int *baud, in imx_uart_console_get_options() argument
2025 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { in imx_uart_console_get_options()
2031 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_console_get_options()
2046 ubir = imx_uart_readl(sport, UBIR) & 0xffff; in imx_uart_console_get_options()
2047 ubmr = imx_uart_readl(sport, UBMR) & 0xffff; in imx_uart_console_get_options()
2049 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; in imx_uart_console_get_options()
2055 uartclk = clk_get_rate(sport->clk_per); in imx_uart_console_get_options()
2074 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", in imx_uart_console_get_options()
2082 struct imx_port *sport; in imx_uart_console_setup() local
2096 sport = imx_uart_ports[co->index]; in imx_uart_console_setup()
2097 if (sport == NULL) in imx_uart_console_setup()
2101 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_console_setup()
2108 imx_uart_console_get_options(sport, &baud, &parity, &bits); in imx_uart_console_setup()
2110 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); in imx_uart_console_setup()
2112 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); in imx_uart_console_setup()
2115 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2119 retval = clk_prepare_enable(sport->clk_per); in imx_uart_console_setup()
2121 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2130 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_exit() local
2132 clk_disable_unprepare(sport->clk_per); in imx_uart_console_exit()
2133 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_exit()
2168 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx); in imx_trigger_start_tx() local
2171 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_start_tx()
2172 if (sport->tx_state == WAIT_AFTER_RTS) in imx_trigger_start_tx()
2173 imx_uart_start_tx(&sport->port); in imx_trigger_start_tx()
2174 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_start_tx()
2181 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx); in imx_trigger_stop_tx() local
2184 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_stop_tx()
2185 if (sport->tx_state == WAIT_AFTER_SEND) in imx_trigger_stop_tx()
2186 imx_uart_stop_tx(&sport->port); in imx_trigger_stop_tx()
2187 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_stop_tx()
2199 struct imx_port *sport; in imx_uart_probe() local
2207 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in imx_uart_probe()
2208 if (!sport) in imx_uart_probe()
2211 sport->devdata = of_device_get_match_data(&pdev->dev); in imx_uart_probe()
2218 sport->port.line = ret; in imx_uart_probe()
2222 sport->have_rtscts = 1; in imx_uart_probe()
2225 sport->dte_mode = 1; in imx_uart_probe()
2228 sport->have_rtsgpio = 1; in imx_uart_probe()
2231 sport->inverted_tx = 1; in imx_uart_probe()
2234 sport->inverted_rx = 1; in imx_uart_probe()
2237 sport->rx_period_length = dma_buf_conf[0]; in imx_uart_probe()
2238 sport->rx_periods = dma_buf_conf[1]; in imx_uart_probe()
2240 sport->rx_period_length = RX_DMA_PERIOD_LEN; in imx_uart_probe()
2241 sport->rx_periods = RX_DMA_PERIODS; in imx_uart_probe()
2244 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { in imx_uart_probe()
2246 sport->port.line); in imx_uart_probe()
2261 sport->port.dev = &pdev->dev; in imx_uart_probe()
2262 sport->port.mapbase = res->start; in imx_uart_probe()
2263 sport->port.membase = base; in imx_uart_probe()
2264 sport->port.type = PORT_IMX; in imx_uart_probe()
2265 sport->port.iotype = UPIO_MEM; in imx_uart_probe()
2266 sport->port.irq = rxirq; in imx_uart_probe()
2267 sport->port.fifosize = 32; in imx_uart_probe()
2268 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); in imx_uart_probe()
2269 sport->port.ops = &imx_uart_pops; in imx_uart_probe()
2270 sport->port.rs485_config = imx_uart_rs485_config; in imx_uart_probe()
2271 sport->port.flags = UPF_BOOT_AUTOCONF; in imx_uart_probe()
2272 timer_setup(&sport->timer, imx_uart_timeout, 0); in imx_uart_probe()
2274 sport->gpios = mctrl_gpio_init(&sport->port, 0); in imx_uart_probe()
2275 if (IS_ERR(sport->gpios)) in imx_uart_probe()
2276 return PTR_ERR(sport->gpios); in imx_uart_probe()
2278 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in imx_uart_probe()
2279 if (IS_ERR(sport->clk_ipg)) { in imx_uart_probe()
2280 ret = PTR_ERR(sport->clk_ipg); in imx_uart_probe()
2285 sport->clk_per = devm_clk_get(&pdev->dev, "per"); in imx_uart_probe()
2286 if (IS_ERR(sport->clk_per)) { in imx_uart_probe()
2287 ret = PTR_ERR(sport->clk_per); in imx_uart_probe()
2292 sport->port.uartclk = clk_get_rate(sport->clk_per); in imx_uart_probe()
2295 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_probe()
2302 sport->ucr1 = readl(sport->port.membase + UCR1); in imx_uart_probe()
2303 sport->ucr2 = readl(sport->port.membase + UCR2); in imx_uart_probe()
2304 sport->ucr3 = readl(sport->port.membase + UCR3); in imx_uart_probe()
2305 sport->ucr4 = readl(sport->port.membase + UCR4); in imx_uart_probe()
2306 sport->ufcr = readl(sport->port.membase + UFCR); in imx_uart_probe()
2308 ret = uart_get_rs485_mode(&sport->port); in imx_uart_probe()
2310 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2314 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2315 (!sport->have_rtscts && !sport->have_rtsgpio)) in imx_uart_probe()
2323 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2324 sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_probe()
2325 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && in imx_uart_probe()
2326 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) in imx_uart_probe()
2330 imx_uart_rs485_config(&sport->port, &sport->port.rs485); in imx_uart_probe()
2333 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_probe()
2335 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_probe()
2337 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { in imx_uart_probe()
2344 u32 ufcr = imx_uart_readl(sport, UFCR); in imx_uart_probe()
2346 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); in imx_uart_probe()
2353 imx_uart_writel(sport, in imx_uart_probe()
2359 u32 ufcr = imx_uart_readl(sport, UFCR); in imx_uart_probe()
2361 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); in imx_uart_probe()
2363 if (!imx_uart_is_imx1(sport)) in imx_uart_probe()
2365 imx_uart_writel(sport, ucr3, UCR3); in imx_uart_probe()
2368 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2370 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2371 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2372 sport->trigger_start_tx.function = imx_trigger_start_tx; in imx_uart_probe()
2373 sport->trigger_stop_tx.function = imx_trigger_stop_tx; in imx_uart_probe()
2381 dev_name(&pdev->dev), sport); in imx_uart_probe()
2389 dev_name(&pdev->dev), sport); in imx_uart_probe()
2397 dev_name(&pdev->dev), sport); in imx_uart_probe()
2405 dev_name(&pdev->dev), sport); in imx_uart_probe()
2412 imx_uart_ports[sport->port.line] = sport; in imx_uart_probe()
2414 platform_set_drvdata(pdev, sport); in imx_uart_probe()
2416 return uart_add_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_probe()
2421 struct imx_port *sport = platform_get_drvdata(pdev); in imx_uart_remove() local
2423 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_remove()
2426 static void imx_uart_restore_context(struct imx_port *sport) in imx_uart_restore_context() argument
2430 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_restore_context()
2431 if (!sport->context_saved) { in imx_uart_restore_context()
2432 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2436 imx_uart_writel(sport, sport->saved_reg[4], UFCR); in imx_uart_restore_context()
2437 imx_uart_writel(sport, sport->saved_reg[5], UESC); in imx_uart_restore_context()
2438 imx_uart_writel(sport, sport->saved_reg[6], UTIM); in imx_uart_restore_context()
2439 imx_uart_writel(sport, sport->saved_reg[7], UBIR); in imx_uart_restore_context()
2440 imx_uart_writel(sport, sport->saved_reg[8], UBMR); in imx_uart_restore_context()
2441 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); in imx_uart_restore_context()
2442 imx_uart_writel(sport, sport->saved_reg[0], UCR1); in imx_uart_restore_context()
2443 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); in imx_uart_restore_context()
2444 imx_uart_writel(sport, sport->saved_reg[2], UCR3); in imx_uart_restore_context()
2445 imx_uart_writel(sport, sport->saved_reg[3], UCR4); in imx_uart_restore_context()
2446 sport->context_saved = false; in imx_uart_restore_context()
2447 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2450 static void imx_uart_save_context(struct imx_port *sport) in imx_uart_save_context() argument
2455 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_save_context()
2456 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); in imx_uart_save_context()
2457 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); in imx_uart_save_context()
2458 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); in imx_uart_save_context()
2459 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); in imx_uart_save_context()
2460 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); in imx_uart_save_context()
2461 sport->saved_reg[5] = imx_uart_readl(sport, UESC); in imx_uart_save_context()
2462 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); in imx_uart_save_context()
2463 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); in imx_uart_save_context()
2464 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); in imx_uart_save_context()
2465 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); in imx_uart_save_context()
2466 sport->context_saved = true; in imx_uart_save_context()
2467 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_save_context()
2470 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) in imx_uart_enable_wakeup() argument
2474 ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_enable_wakeup()
2476 imx_uart_writel(sport, USR1_AWAKE, USR1); in imx_uart_enable_wakeup()
2481 imx_uart_writel(sport, ucr3, UCR3); in imx_uart_enable_wakeup()
2483 if (sport->have_rtscts) { in imx_uart_enable_wakeup()
2484 u32 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_enable_wakeup()
2489 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_enable_wakeup()
2495 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_suspend_noirq() local
2497 imx_uart_save_context(sport); in imx_uart_suspend_noirq()
2499 clk_disable(sport->clk_ipg); in imx_uart_suspend_noirq()
2508 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_resume_noirq() local
2513 ret = clk_enable(sport->clk_ipg); in imx_uart_resume_noirq()
2517 imx_uart_restore_context(sport); in imx_uart_resume_noirq()
2524 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_suspend() local
2527 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_suspend()
2528 disable_irq(sport->port.irq); in imx_uart_suspend()
2530 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_suspend()
2535 imx_uart_enable_wakeup(sport, true); in imx_uart_suspend()
2542 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_resume() local
2545 imx_uart_enable_wakeup(sport, false); in imx_uart_resume()
2547 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_resume()
2548 enable_irq(sport->port.irq); in imx_uart_resume()
2550 clk_disable_unprepare(sport->clk_ipg); in imx_uart_resume()
2557 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_freeze() local
2559 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_freeze()
2561 return clk_prepare_enable(sport->clk_ipg); in imx_uart_freeze()
2566 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_thaw() local
2568 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_thaw()
2570 clk_disable_unprepare(sport->clk_ipg); in imx_uart_thaw()