Lines Matching refs:ch_cls_uart
54 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
55 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_cts_flow_control()
62 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
64 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
70 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
73 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
81 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_cts_flow_control()
84 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
88 &ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
95 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_ixon_flow_control()
96 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_ixon_flow_control()
103 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_ixon_flow_control()
105 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
111 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
114 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); in cls_set_ixon_flow_control()
115 writeb(0, &ch->ch_cls_uart->lsr); in cls_set_ixon_flow_control()
116 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); in cls_set_ixon_flow_control()
117 writeb(0, &ch->ch_cls_uart->spr); in cls_set_ixon_flow_control()
120 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_ixon_flow_control()
128 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_ixon_flow_control()
131 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
135 &ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
140 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_no_output_flow_control()
141 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_no_output_flow_control()
148 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_no_output_flow_control()
150 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
156 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
159 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_no_output_flow_control()
167 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_no_output_flow_control()
170 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
174 &ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
183 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_rts_flow_control()
184 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_rts_flow_control()
191 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_rts_flow_control()
193 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
199 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
202 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_rts_flow_control()
206 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_rts_flow_control()
209 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
213 &ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
221 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_ixoff_flow_control()
222 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_ixoff_flow_control()
229 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_ixoff_flow_control()
231 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
237 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
240 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); in cls_set_ixoff_flow_control()
241 writeb(0, &ch->ch_cls_uart->lsr); in cls_set_ixoff_flow_control()
242 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); in cls_set_ixoff_flow_control()
243 writeb(0, &ch->ch_cls_uart->spr); in cls_set_ixoff_flow_control()
246 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_ixoff_flow_control()
250 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_ixoff_flow_control()
253 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
257 &ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
262 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_no_input_flow_control()
263 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_no_input_flow_control()
270 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_no_input_flow_control()
272 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
278 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
281 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_no_input_flow_control()
285 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_no_input_flow_control()
288 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
292 &ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
313 u8 temp = readb(&ch->ch_cls_uart->lcr); in cls_clear_break()
315 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr); in cls_clear_break()
327 u8 tmp = readb(&ch->ch_cls_uart->ier); in cls_disable_receiver()
330 writeb(tmp, &ch->ch_cls_uart->ier); in cls_disable_receiver()
335 u8 tmp = readb(&ch->ch_cls_uart->ier); in cls_enable_receiver()
338 writeb(tmp, &ch->ch_cls_uart->ier); in cls_enable_receiver()
347 writeb(ch->ch_mostat, &ch->ch_cls_uart->mcr); in cls_assert_modem_signals()
389 linestatus = readb(&ch->ch_cls_uart->lsr); in cls_copy_data_from_uart_to_queue()
401 readb(&ch->ch_cls_uart->txrx); in cls_copy_data_from_uart_to_queue()
422 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx); in cls_copy_data_from_uart_to_queue()
482 writeb(circ->buf[tail], &ch->ch_cls_uart->txrx); in cls_copy_data_from_queue_to_uart()
571 isr = readb(&ch->ch_cls_uart->isr_fcr); in cls_parse_isr()
600 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr)); in cls_parse_isr()
614 &ch->ch_cls_uart->isr_fcr); in cls_flush_uart_write()
618 tmp = readb(&ch->ch_cls_uart->isr_fcr); in cls_flush_uart_write()
657 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx); in cls_send_start_character()
668 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx); in cls_send_stop_character()
756 ier = readb(&ch->ch_cls_uart->ier); in cls_param()
757 uart_lcr = readb(&ch->ch_cls_uart->lcr); in cls_param()
762 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr); in cls_param()
763 writeb((quot & 0xff), &ch->ch_cls_uart->txrx); in cls_param()
764 writeb((quot >> 8), &ch->ch_cls_uart->ier); in cls_param()
765 writeb(lcr, &ch->ch_cls_uart->lcr); in cls_param()
769 writeb(lcr, &ch->ch_cls_uart->lcr); in cls_param()
776 writeb(ier, &ch->ch_cls_uart->ier); in cls_param()
811 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr)); in cls_param()
859 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); in cls_uart_init()
862 writeb(0, &ch->ch_cls_uart->ier); in cls_uart_init()
868 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_uart_init()
870 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_uart_init()
875 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_uart_init()
878 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_uart_init()
881 readb(&ch->ch_cls_uart->txrx); in cls_uart_init()
884 &ch->ch_cls_uart->isr_fcr); in cls_uart_init()
889 readb(&ch->ch_cls_uart->lsr); in cls_uart_init()
890 readb(&ch->ch_cls_uart->msr); in cls_uart_init()
899 writeb(0, &ch->ch_cls_uart->ier); in cls_uart_off()
911 u8 lsr = readb(&ch->ch_cls_uart->lsr); in cls_get_uart_bytes_left()
934 u8 temp = readb(&ch->ch_cls_uart->lcr); in cls_send_break()
936 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr); in cls_send_break()
950 writeb(c, &ch->ch_cls_uart->txrx); in cls_send_immediate_char()