Lines Matching refs:R5
142 write_zsreg(uap, R5, regs[R5] & ~TxENABLE); in pmz_load_zsregs()
174 write_zsreg(uap, R5, regs[R5]); in pmz_load_zsregs()
564 uap->curregs[R5] |= set_bits; in pmz_set_mctrl()
565 uap->curregs[R5] &= ~clear_bits; in pmz_set_mctrl()
567 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_set_mctrl()
569 set_bits, clear_bits, uap->curregs[R5]); in pmz_set_mctrl()
710 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; in pmz_break_ctl()
711 if (new_reg != uap->curregs[R5]) { in pmz_break_ctl()
712 uap->curregs[R5] = new_reg; in pmz_break_ctl()
713 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_break_ctl()
859 uap->curregs[R5] = Tx8 | RTS; in __pmz_startup()
861 uap->curregs[R5] |= DTR; in __pmz_startup()
876 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE); in __pmz_startup()
889 uap->curregs[R5] |= DTR; in pmz_irda_reset()
890 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_reset()
896 uap->curregs[R5] &= ~DTR; in pmz_irda_reset()
897 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_reset()
970 uap->curregs[R5] &= ~TxENABLE; in pmz_shutdown()
973 uap->curregs[R5] &= ~SND_BRK; in pmz_shutdown()
1170 uap->curregs[R5] |= DTR; in pmz_irda_setup()
1171 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_setup()
1220 uap->curregs[R5] &= ~DTR; in pmz_irda_setup()
1221 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_setup()
1967 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR); in pmz_console_write()