Lines Matching refs:dev_vdbg
414 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); in dwc2_read_packet()
532 dev_vdbg(hsotg->dev, "control/bulk\n"); in dwc2_hc_enable_slave_ints()
560 dev_vdbg(hsotg->dev, "intr\n"); in dwc2_hc_enable_slave_ints()
582 dev_vdbg(hsotg->dev, "isoc\n"); in dwc2_hc_enable_slave_ints()
599 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); in dwc2_hc_enable_slave_ints()
613 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); in dwc2_hc_enable_dma_ints()
617 dev_vdbg(hsotg->dev, "desc DMA enabled\n"); in dwc2_hc_enable_dma_ints()
625 dev_vdbg(hsotg->dev, "setting ACK\n"); in dwc2_hc_enable_dma_ints()
636 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); in dwc2_hc_enable_dma_ints()
646 dev_vdbg(hsotg->dev, "DMA enabled\n"); in dwc2_hc_enable_ints()
650 dev_vdbg(hsotg->dev, "DMA disabled\n"); in dwc2_hc_enable_ints()
659 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); in dwc2_hc_enable_ints()
666 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); in dwc2_hc_enable_ints()
688 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_hc_init()
712 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", in dwc2_hc_init()
715 dev_vdbg(hsotg->dev, "%s: Channel %d\n", in dwc2_hc_init()
717 dev_vdbg(hsotg->dev, " Dev Addr: %d\n", in dwc2_hc_init()
719 dev_vdbg(hsotg->dev, " Ep Num: %d\n", in dwc2_hc_init()
721 dev_vdbg(hsotg->dev, " Is In: %d\n", in dwc2_hc_init()
723 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", in dwc2_hc_init()
725 dev_vdbg(hsotg->dev, " Ep Type: %d\n", in dwc2_hc_init()
727 dev_vdbg(hsotg->dev, " Max Pkt: %d\n", in dwc2_hc_init()
734 dev_vdbg(hsotg->dev, in dwc2_hc_init()
747 dev_vdbg(hsotg->dev, " comp split %d\n", in dwc2_hc_init()
749 dev_vdbg(hsotg->dev, " xact pos %d\n", in dwc2_hc_init()
751 dev_vdbg(hsotg->dev, " hub addr %d\n", in dwc2_hc_init()
753 dev_vdbg(hsotg->dev, " hub port %d\n", in dwc2_hc_init()
755 dev_vdbg(hsotg->dev, " is_in %d\n", in dwc2_hc_init()
757 dev_vdbg(hsotg->dev, " Max Pkt %d\n", in dwc2_hc_init()
759 dev_vdbg(hsotg->dev, " xferlen %d\n", in dwc2_hc_init()
801 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_hc_halt()
833 dev_vdbg(hsotg->dev, "dequeue/error\n"); in dwc2_hc_halt()
872 dev_vdbg(hsotg->dev, in dwc2_hc_halt()
884 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); in dwc2_hc_halt()
894 dev_vdbg(hsotg->dev, "DMA not enabled\n"); in dwc2_hc_halt()
900 dev_vdbg(hsotg->dev, "control/bulk\n"); in dwc2_hc_halt()
903 dev_vdbg(hsotg->dev, "Disabling channel\n"); in dwc2_hc_halt()
908 dev_vdbg(hsotg->dev, "isoc/intr\n"); in dwc2_hc_halt()
913 dev_vdbg(hsotg->dev, "Disabling channel\n"); in dwc2_hc_halt()
919 dev_vdbg(hsotg->dev, "DMA enabled\n"); in dwc2_hc_halt()
927 dev_vdbg(hsotg->dev, "Channel enabled\n"); in dwc2_hc_halt()
932 dev_vdbg(hsotg->dev, "Channel disabled\n"); in dwc2_hc_halt()
937 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_halt()
939 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", in dwc2_hc_halt()
941 dev_vdbg(hsotg->dev, " halt_pending: %d\n", in dwc2_hc_halt()
943 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", in dwc2_hc_halt()
945 dev_vdbg(hsotg->dev, " halt_status: %d\n", in dwc2_hc_halt()
1132 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_hc_write_packet()
1175 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_do_ping()
1232 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_hc_start_transfer()
1237 dev_vdbg(hsotg->dev, "ping, no DMA\n"); in dwc2_hc_start_transfer()
1244 dev_vdbg(hsotg->dev, "ping, DMA\n"); in dwc2_hc_start_transfer()
1251 dev_vdbg(hsotg->dev, "split\n"); in dwc2_hc_start_transfer()
1276 dev_vdbg(hsotg->dev, "no split\n"); in dwc2_hc_start_transfer()
1348 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", in dwc2_hc_start_transfer()
1351 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_start_transfer()
1353 dev_vdbg(hsotg->dev, " Xfer Size: %d\n", in dwc2_hc_start_transfer()
1356 dev_vdbg(hsotg->dev, " Num Pkts: %d\n", in dwc2_hc_start_transfer()
1359 dev_vdbg(hsotg->dev, " Start PID: %d\n", in dwc2_hc_start_transfer()
1369 dev_vdbg(hsotg->dev, "align_buf\n"); in dwc2_hc_start_transfer()
1377 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", in dwc2_hc_start_transfer()
1404 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", in dwc2_hc_start_transfer()
1410 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, in dwc2_hc_start_transfer()
1459 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_start_transfer_ddma()
1461 dev_vdbg(hsotg->dev, " Start PID: %d\n", in dwc2_hc_start_transfer_ddma()
1463 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); in dwc2_hc_start_transfer_ddma()
1474 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", in dwc2_hc_start_transfer_ddma()
1492 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", in dwc2_hc_start_transfer_ddma()
1498 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, in dwc2_hc_start_transfer_ddma()
1529 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, in dwc2_hc_continue_transfer()
1559 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", in dwc2_hc_continue_transfer()
2361 dev_vdbg(hsotg->dev, " Control setup transaction\n"); in dwc2_hc_init_xfer()
2373 dev_vdbg(hsotg->dev, " Control data transaction\n"); in dwc2_hc_init_xfer()
2382 dev_vdbg(hsotg->dev, " Control status transaction\n"); in dwc2_hc_init_xfer()
2580 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); in dwc2_assign_and_init_hc()
2659 dev_vdbg(hsotg->dev, "Non-aligned buffer\n"); in dwc2_assign_and_init_hc()
2719 dev_vdbg(hsotg->dev, " Select Transactions\n"); in dwc2_hcd_select_transactions()
2890 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); in dwc2_process_periodic_channels()
2899 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", in dwc2_process_periodic_channels()
2901 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", in dwc2_process_periodic_channels()
3020 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); in dwc2_process_non_periodic_channels()
3027 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", in dwc2_process_non_periodic_channels()
3029 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", in dwc2_process_non_periodic_channels()
3087 dev_vdbg(hsotg->dev, in dwc2_process_non_periodic_channels()
3090 dev_vdbg(hsotg->dev, in dwc2_process_non_periodic_channels()
3135 dev_vdbg(hsotg->dev, "Queue Transactions\n"); in dwc2_hcd_queue_transactions()
3550 dev_vdbg(hsotg->dev, in dwc2_hcd_hub_control()
3585 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); in dwc2_hcd_hub_control()
3632 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); in dwc2_hcd_hub_control()
3807 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", in dwc2_hcd_get_frame_number()
3867 dev_vdbg(hsotg->dev, in dwc2_hcd_urb_set_pipeinfo()
4167 dev_vdbg(hsotg->dev, in dwc2_host_complete()
4187 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", in dwc2_host_complete()
4564 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); in dwc2_dump_urb_info()
4565 dev_vdbg(hsotg->dev, " Device address: %d\n", in dwc2_dump_urb_info()
4567 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", in dwc2_dump_urb_info()
4586 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, in dwc2_dump_urb_info()
4605 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); in dwc2_dump_urb_info()
4606 dev_vdbg(hsotg->dev, " Max packet size: %d (%d mult)\n", in dwc2_dump_urb_info()
4610 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", in dwc2_dump_urb_info()
4612 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", in dwc2_dump_urb_info()
4614 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", in dwc2_dump_urb_info()
4616 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); in dwc2_dump_urb_info()
4622 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); in dwc2_dump_urb_info()
4623 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", in dwc2_dump_urb_info()
4657 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); in _dwc2_hcd_urb_enqueue()