Lines Matching refs:writel_relaxed

42 			writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR);  in ctrl_handle_irq()
126 	writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));  in dmafetch_set_fmt()
139 		writel_relaxed(win->pitch[0],  in overlay_set_win()
141 		writel_relaxed(win->pitch[2] << 16 | win->pitch[1],  in overlay_set_win()
144 		writel_relaxed((win->ysrc << 16) | win->xsrc,  in overlay_set_win()
146 		writel_relaxed((win->ydst << 16) | win->xdst,  in overlay_set_win()
148 		writel_relaxed(win->ypos << 16 | win->xpos,  in overlay_set_win()
151 		writel_relaxed(win->pitch[0], (void __iomem *)&regs->g_pitch);  in overlay_set_win()
153 		writel_relaxed((win->ysrc << 16) | win->xsrc,  in overlay_set_win()
155 		writel_relaxed((win->ydst << 16) | win->xdst,  in overlay_set_win()
157 		writel_relaxed(win->ypos << 16 | win->xpos,  in overlay_set_win()
190 	writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));  in path_enabledisable()
243 		writel_relaxed(addr->phys[0], (void __iomem *)&regs->v_y0);  in overlay_set_addr()
244 		writel_relaxed(addr->phys[1], (void __iomem *)&regs->v_u0);  in overlay_set_addr()
245 		writel_relaxed(addr->phys[2], (void __iomem *)&regs->v_v0);  in overlay_set_addr()
247 		writel_relaxed(addr->phys[0], (void __iomem *)&regs->g_0);  in overlay_set_addr()
270 	writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id));  in path_set_mode()
276 	writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id));  in path_set_mode()
278 	writel_relaxed((mode->yres << 16) | mode->xres,  in path_set_mode()
280 	writel_relaxed((mode->left_margin << 16) | mode->right_margin,  in path_set_mode()
282 	writel_relaxed((mode->upper_margin << 16) | mode->lower_margin,  in path_set_mode()
288 	writel_relaxed((total_y << 16) | total_x,  in path_set_mode()
297 	writel_relaxed(vsync_ctrl, (void __iomem *)&regs->vsync_ctrl);  in path_set_mode()
311 	writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));  in path_set_mode()
333 	writel_relaxed(tmp, ctrl->reg_base + LCD_TOP_CTRL);  in ctrl_set_default()
342 	writel_relaxed(tmp, ctrl->reg_base + SPU_IRQ_ENA);  in ctrl_set_default()
358 		writel_relaxed(tmp, ctrl_regs(path) + SPU_IOPAD_CONTROL);  in path_set_default()
365 	writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));  in path_set_default()
375 	writel_relaxed(dma_ctrl1, ctrl_regs(path) + dma_ctrl(1, path->id));  in path_set_default()
378 	writel_relaxed(0x00000000, (void __iomem *)&regs->blank_color);  in path_set_default()
379 	writel_relaxed(0x00000000, (void __iomem *)&regs->g_1);  in path_set_default()
380 	writel_relaxed(0x00000000, (void __iomem *)&regs->g_start);  in path_set_default()
392 	writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));  in path_set_default()