Lines Matching refs:par
191 static u8 s3fb_ddc_read(struct s3fb_info *par) in s3fb_ddc_read() argument
193 if (s3fb_ddc_needs_mmio(par->chip)) in s3fb_ddc_read()
194 return readb(par->mmio + DDC_MMIO_REG); in s3fb_ddc_read()
196 return vga_rcrt(par->state.vgabase, DDC_REG); in s3fb_ddc_read()
199 static void s3fb_ddc_write(struct s3fb_info *par, u8 val) in s3fb_ddc_write() argument
201 if (s3fb_ddc_needs_mmio(par->chip)) in s3fb_ddc_write()
202 writeb(val, par->mmio + DDC_MMIO_REG); in s3fb_ddc_write()
204 vga_wcrt(par->state.vgabase, DDC_REG, val); in s3fb_ddc_write()
209 struct s3fb_info *par = data; in s3fb_ddc_setscl() local
212 reg = s3fb_ddc_read(par) | DDC_DRIVE_EN; in s3fb_ddc_setscl()
217 s3fb_ddc_write(par, reg); in s3fb_ddc_setscl()
222 struct s3fb_info *par = data; in s3fb_ddc_setsda() local
225 reg = s3fb_ddc_read(par) | DDC_DRIVE_EN; in s3fb_ddc_setsda()
230 s3fb_ddc_write(par, reg); in s3fb_ddc_setsda()
235 struct s3fb_info *par = data; in s3fb_ddc_getscl() local
237 return !!(s3fb_ddc_read(par) & DDC_SCL_IN); in s3fb_ddc_getscl()
242 struct s3fb_info *par = data; in s3fb_ddc_getsda() local
244 return !!(s3fb_ddc_read(par) & DDC_SDA_IN); in s3fb_ddc_getsda()
249 struct s3fb_info *par = info->par; in s3fb_setup_ddc_bus() local
251 strlcpy(par->ddc_adapter.name, info->fix.id, in s3fb_setup_ddc_bus()
252 sizeof(par->ddc_adapter.name)); in s3fb_setup_ddc_bus()
253 par->ddc_adapter.owner = THIS_MODULE; in s3fb_setup_ddc_bus()
254 par->ddc_adapter.class = I2C_CLASS_DDC; in s3fb_setup_ddc_bus()
255 par->ddc_adapter.algo_data = &par->ddc_algo; in s3fb_setup_ddc_bus()
256 par->ddc_adapter.dev.parent = info->device; in s3fb_setup_ddc_bus()
257 par->ddc_algo.setsda = s3fb_ddc_setsda; in s3fb_setup_ddc_bus()
258 par->ddc_algo.setscl = s3fb_ddc_setscl; in s3fb_setup_ddc_bus()
259 par->ddc_algo.getsda = s3fb_ddc_getsda; in s3fb_setup_ddc_bus()
260 par->ddc_algo.getscl = s3fb_ddc_getscl; in s3fb_setup_ddc_bus()
261 par->ddc_algo.udelay = 10; in s3fb_setup_ddc_bus()
262 par->ddc_algo.timeout = 20; in s3fb_setup_ddc_bus()
263 par->ddc_algo.data = par; in s3fb_setup_ddc_bus()
265 i2c_set_adapdata(&par->ddc_adapter, par); in s3fb_setup_ddc_bus()
272 if (par->chip == CHIP_357_VIRGE_GX2 || in s3fb_setup_ddc_bus()
273 par->chip == CHIP_359_VIRGE_GX2P || in s3fb_setup_ddc_bus()
274 par->chip == CHIP_260_VIRGE_MX) in s3fb_setup_ddc_bus()
275 svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03); in s3fb_setup_ddc_bus()
277 svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03); in s3fb_setup_ddc_bus()
279 svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03); in s3fb_setup_ddc_bus()
281 return i2c_bit_add_bus(&par->ddc_adapter); in s3fb_setup_ddc_bus()
314 struct s3fb_info *par = info->par; in s3fb_tilecursor() local
316 svga_tilecursor(par->state.vgabase, info, cursor); in s3fb_tilecursor()
460 struct s3fb_info *par = info->par; in s3_set_pixclock() local
465 rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll, in s3_set_pixclock()
473 regval = vga_r(par->state.vgabase, VGA_MIS_R); in s3_set_pixclock()
474 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); in s3_set_pixclock()
477 if (par->chip == CHIP_357_VIRGE_GX2 || in s3_set_pixclock()
478 par->chip == CHIP_359_VIRGE_GX2P || in s3_set_pixclock()
479 par->chip == CHIP_360_TRIO3D_1X || in s3_set_pixclock()
480 par->chip == CHIP_362_TRIO3D_2X || in s3_set_pixclock()
481 par->chip == CHIP_368_TRIO3D_2X || in s3_set_pixclock()
482 par->chip == CHIP_260_VIRGE_MX) { in s3_set_pixclock()
483 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ in s3_set_pixclock()
484 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */ in s3_set_pixclock()
486 vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5)); in s3_set_pixclock()
487 vga_wseq(par->state.vgabase, 0x13, m - 2); in s3_set_pixclock()
492 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ in s3_set_pixclock()
493 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); in s3_set_pixclock()
494 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); in s3_set_pixclock()
495 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); in s3_set_pixclock()
503 struct s3fb_info *par = info->par; in s3fb_open() local
505 mutex_lock(&(par->open_lock)); in s3fb_open()
506 if (par->ref_count == 0) { in s3fb_open()
507 void __iomem *vgabase = par->state.vgabase; in s3fb_open()
509 memset(&(par->state), 0, sizeof(struct vgastate)); in s3fb_open()
510 par->state.vgabase = vgabase; in s3fb_open()
511 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; in s3fb_open()
512 par->state.num_crtc = 0x70; in s3fb_open()
513 par->state.num_seq = 0x20; in s3fb_open()
514 save_vga(&(par->state)); in s3fb_open()
517 par->ref_count++; in s3fb_open()
518 mutex_unlock(&(par->open_lock)); in s3fb_open()
527 struct s3fb_info *par = info->par; in s3fb_release() local
529 mutex_lock(&(par->open_lock)); in s3fb_release()
530 if (par->ref_count == 0) { in s3fb_release()
531 mutex_unlock(&(par->open_lock)); in s3fb_release()
535 if (par->ref_count == 1) in s3fb_release()
536 restore_vga(&(par->state)); in s3fb_release()
538 par->ref_count--; in s3fb_release()
539 mutex_unlock(&(par->open_lock)); in s3fb_release()
548 struct s3fb_info *par = info->par; in s3fb_check_var() local
557 if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6)) in s3fb_check_var()
604 struct s3fb_info *par = info->par; in s3fb_set_par() local
642 vga_wcrt(par->state.vgabase, 0x38, 0x48); in s3fb_set_par()
643 vga_wcrt(par->state.vgabase, 0x39, 0xA5); in s3fb_set_par()
644 vga_wseq(par->state.vgabase, 0x08, 0x06); in s3fb_set_par()
645 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); in s3fb_set_par()
648 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_set_par()
649 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); in s3fb_set_par()
652 svga_set_default_gfx_regs(par->state.vgabase); in s3fb_set_par()
653 svga_set_default_atc_regs(par->state.vgabase); in s3fb_set_par()
654 svga_set_default_seq_regs(par->state.vgabase); in s3fb_set_par()
655 svga_set_default_crt_regs(par->state.vgabase); in s3fb_set_par()
656 svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF); in s3fb_set_par()
657 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0); in s3fb_set_par()
660 svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */ in s3fb_set_par()
661 …svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer ab… in s3fb_set_par()
665 svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */ in s3fb_set_par()
666 svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */ in s3fb_set_par()
668 svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */ in s3fb_set_par()
678 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value); in s3fb_set_par()
680 if (par->chip != CHIP_357_VIRGE_GX2 && in s3fb_set_par()
681 par->chip != CHIP_359_VIRGE_GX2P && in s3fb_set_par()
682 par->chip != CHIP_360_TRIO3D_1X && in s3fb_set_par()
683 par->chip != CHIP_362_TRIO3D_2X && in s3fb_set_par()
684 par->chip != CHIP_368_TRIO3D_2X && in s3fb_set_par()
685 par->chip != CHIP_260_VIRGE_MX) { in s3fb_set_par()
686 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */ in s3fb_set_par()
687 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */ in s3fb_set_par()
688 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */ in s3fb_set_par()
689 vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */ in s3fb_set_par()
692 vga_wcrt(par->state.vgabase, 0x3A, 0x35); in s3fb_set_par()
693 svga_wattr(par->state.vgabase, 0x33, 0x00); in s3fb_set_par()
696 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); in s3fb_set_par()
698 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); in s3fb_set_par()
701 svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20); in s3fb_set_par()
703 svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20); in s3fb_set_par()
706 svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01); in s3fb_set_par()
708 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C); in s3fb_set_par()
713 if (par->chip == CHIP_375_VIRGE_DX) { in s3fb_set_par()
714 vga_wcrt(par->state.vgabase, 0x86, 0x80); in s3fb_set_par()
715 vga_wcrt(par->state.vgabase, 0x90, 0x00); in s3fb_set_par()
719 if (par->chip == CHIP_988_VIRGE_VX) { in s3fb_set_par()
720 vga_wcrt(par->state.vgabase, 0x50, 0x00); in s3fb_set_par()
721 vga_wcrt(par->state.vgabase, 0x67, 0x50); in s3fb_set_par()
723 vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09); in s3fb_set_par()
724 vga_wcrt(par->state.vgabase, 0x66, 0x90); in s3fb_set_par()
727 if (par->chip == CHIP_357_VIRGE_GX2 || in s3fb_set_par()
728 par->chip == CHIP_359_VIRGE_GX2P || in s3fb_set_par()
729 par->chip == CHIP_360_TRIO3D_1X || in s3fb_set_par()
730 par->chip == CHIP_362_TRIO3D_2X || in s3fb_set_par()
731 par->chip == CHIP_368_TRIO3D_2X || in s3fb_set_par()
732 par->chip == CHIP_365_TRIO3D || in s3fb_set_par()
733 par->chip == CHIP_375_VIRGE_DX || in s3fb_set_par()
734 par->chip == CHIP_385_VIRGE_GX || in s3fb_set_par()
735 par->chip == CHIP_260_VIRGE_MX) { in s3fb_set_par()
737 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8); in s3fb_set_par()
738 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); in s3fb_set_par()
740 vga_wcrt(par->state.vgabase, 0x66, 0x81); in s3fb_set_par()
743 if (par->chip == CHIP_357_VIRGE_GX2 || in s3fb_set_par()
744 par->chip == CHIP_359_VIRGE_GX2P || in s3fb_set_par()
745 par->chip == CHIP_360_TRIO3D_1X || in s3fb_set_par()
746 par->chip == CHIP_362_TRIO3D_2X || in s3fb_set_par()
747 par->chip == CHIP_368_TRIO3D_2X || in s3fb_set_par()
748 par->chip == CHIP_260_VIRGE_MX) in s3fb_set_par()
749 vga_wcrt(par->state.vgabase, 0x34, 0x00); in s3fb_set_par()
751 vga_wcrt(par->state.vgabase, 0x34, 0x10); in s3fb_set_par()
753 svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40); in s3fb_set_par()
761 svga_set_textmode_vga_regs(par->state.vgabase); in s3fb_set_par()
764 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
765 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
768 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
772 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40); in s3fb_set_par()
777 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); in s3fb_set_par()
780 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
781 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
784 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
790 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
791 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
794 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
798 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
800 par->chip == CHIP_357_VIRGE_GX2 || in s3fb_set_par()
801 par->chip == CHIP_359_VIRGE_GX2P || in s3fb_set_par()
802 par->chip == CHIP_360_TRIO3D_1X || in s3fb_set_par()
803 par->chip == CHIP_362_TRIO3D_2X || in s3fb_set_par()
804 par->chip == CHIP_368_TRIO3D_2X || in s3fb_set_par()
805 par->chip == CHIP_260_VIRGE_MX) in s3fb_set_par()
806 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
808 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0); in s3fb_set_par()
814 if (par->chip == CHIP_988_VIRGE_VX) { in s3fb_set_par()
816 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); in s3fb_set_par()
818 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
819 } else if (par->chip == CHIP_365_TRIO3D) { in s3fb_set_par()
820 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
822 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
825 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); in s3fb_set_par()
829 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
830 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
831 if (par->chip != CHIP_357_VIRGE_GX2 && in s3fb_set_par()
832 par->chip != CHIP_359_VIRGE_GX2P && in s3fb_set_par()
833 par->chip != CHIP_360_TRIO3D_1X && in s3fb_set_par()
834 par->chip != CHIP_362_TRIO3D_2X && in s3fb_set_par()
835 par->chip != CHIP_368_TRIO3D_2X && in s3fb_set_par()
836 par->chip != CHIP_260_VIRGE_MX) in s3fb_set_par()
842 if (par->chip == CHIP_988_VIRGE_VX) { in s3fb_set_par()
844 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); in s3fb_set_par()
846 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
847 } else if (par->chip == CHIP_365_TRIO3D) { in s3fb_set_par()
848 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
850 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
853 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); in s3fb_set_par()
857 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
858 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
859 if (par->chip != CHIP_357_VIRGE_GX2 && in s3fb_set_par()
860 par->chip != CHIP_359_VIRGE_GX2P && in s3fb_set_par()
861 par->chip != CHIP_360_TRIO3D_1X && in s3fb_set_par()
862 par->chip != CHIP_362_TRIO3D_2X && in s3fb_set_par()
863 par->chip != CHIP_368_TRIO3D_2X && in s3fb_set_par()
864 par->chip != CHIP_260_VIRGE_MX) in s3fb_set_par()
871 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); in s3fb_set_par()
875 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30); in s3fb_set_par()
876 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); in s3fb_set_par()
883 if (par->chip != CHIP_988_VIRGE_VX) { in s3fb_set_par()
884 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10); in s3fb_set_par()
885 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80); in s3fb_set_par()
889 svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1, in s3fb_set_par()
897 vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2); in s3fb_set_par()
903 svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value); in s3fb_set_par()
907 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); in s3fb_set_par()
908 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); in s3fb_set_par()
978 struct s3fb_info *par = info->par; in s3fb_blank() local
983 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); in s3fb_blank()
984 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); in s3fb_blank()
988 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); in s3fb_blank()
989 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
993 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06); in s3fb_blank()
994 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
998 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06); in s3fb_blank()
999 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1003 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06); in s3fb_blank()
1004 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1016 struct s3fb_info *par = info->par; in s3fb_pan_display() local
1031 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset); in s3fb_pan_display()
1057 static int s3_identification(struct s3fb_info *par) in s3_identification() argument
1059 int chip = par->chip; in s3_identification()
1062 u8 cr30 = vga_rcrt(par->state.vgabase, 0x30); in s3_identification()
1063 u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e); in s3_identification()
1064 u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f); in s3_identification()
1079 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); in s3_identification()
1088 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); in s3_identification()
1097 switch (vga_rcrt(par->state.vgabase, 0x2f)) { in s3_identification()
1118 struct s3fb_info *par; in s3_pci_probe() local
1134 par = info->par; in s3_pci_probe()
1135 mutex_init(&par->open_lock); in s3_pci_probe()
1172 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start; in s3_pci_probe()
1175 cr38 = vga_rcrt(par->state.vgabase, 0x38); in s3_pci_probe()
1176 cr39 = vga_rcrt(par->state.vgabase, 0x39); in s3_pci_probe()
1177 vga_wseq(par->state.vgabase, 0x08, 0x06); in s3_pci_probe()
1178 vga_wcrt(par->state.vgabase, 0x38, 0x48); in s3_pci_probe()
1179 vga_wcrt(par->state.vgabase, 0x39, 0xA5); in s3_pci_probe()
1182 par->chip = id->driver_data & CHIP_MASK; in s3_pci_probe()
1183 par->rev = vga_rcrt(par->state.vgabase, 0x2f); in s3_pci_probe()
1184 if (par->chip & CHIP_UNDECIDED_FLAG) in s3_pci_probe()
1185 par->chip = s3_identification(par); in s3_pci_probe()
1189 regval = vga_rcrt(par->state.vgabase, 0x36); in s3_pci_probe()
1190 if (par->chip == CHIP_360_TRIO3D_1X || in s3_pci_probe()
1191 par->chip == CHIP_362_TRIO3D_2X || in s3_pci_probe()
1192 par->chip == CHIP_368_TRIO3D_2X || in s3_pci_probe()
1193 par->chip == CHIP_365_TRIO3D) { in s3_pci_probe()
1205 } else if (par->chip == CHIP_357_VIRGE_GX2 || in s3_pci_probe()
1206 par->chip == CHIP_359_VIRGE_GX2P || in s3_pci_probe()
1207 par->chip == CHIP_260_VIRGE_MX) { in s3_pci_probe()
1216 } else if (par->chip == CHIP_988_VIRGE_VX) { in s3_pci_probe()
1232 regval = vga_rcrt(par->state.vgabase, 0x37); in s3_pci_probe()
1246 regval = vga_rseq(par->state.vgabase, 0x10); in s3_pci_probe()
1247 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); in s3_pci_probe()
1248 par->mclk_freq = par->mclk_freq >> (regval >> 5); in s3_pci_probe()
1251 vga_wcrt(par->state.vgabase, 0x38, cr38); in s3_pci_probe()
1252 vga_wcrt(par->state.vgabase, 0x39, cr39); in s3_pci_probe()
1254 strcpy(info->fix.id, s3_names [par->chip]); in s3_pci_probe()
1261 info->pseudo_palette = (void*) (par->pseudo_palette); in s3_pci_probe()
1266 if (s3fb_ddc_needs_mmio(par->chip)) { in s3_pci_probe()
1267 par->mmio = ioremap(info->fix.smem_start + MMIO_OFFSET, MMIO_SIZE); in s3_pci_probe()
1268 if (par->mmio) in s3_pci_probe()
1269 svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */ in s3_pci_probe()
1274 if (!s3fb_ddc_needs_mmio(par->chip) || par->mmio) in s3_pci_probe()
1276 u8 *edid = fb_ddc_read(&par->ddc_adapter); in s3_pci_probe()
1277 par->ddc_registered = true; in s3_pci_probe()
1343 info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000); in s3_pci_probe()
1345 if (par->chip == CHIP_UNKNOWN) in s3_pci_probe()
1347 vga_rcrt(par->state.vgabase, 0x2d), in s3_pci_probe()
1348 vga_rcrt(par->state.vgabase, 0x2e), in s3_pci_probe()
1349 vga_rcrt(par->state.vgabase, 0x2f), in s3_pci_probe()
1350 vga_rcrt(par->state.vgabase, 0x30)); in s3_pci_probe()
1356 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start, in s3_pci_probe()
1367 if (par->ddc_registered) in s3_pci_probe()
1368 i2c_del_adapter(&par->ddc_adapter); in s3_pci_probe()
1369 if (par->mmio) in s3_pci_probe()
1370 iounmap(par->mmio); in s3_pci_probe()
1388 struct s3fb_info __maybe_unused *par; in s3_pci_remove() local
1391 par = info->par; in s3_pci_remove()
1392 arch_phys_wc_del(par->wc_cookie); in s3_pci_remove()
1397 if (par->ddc_registered) in s3_pci_remove()
1398 i2c_del_adapter(&par->ddc_adapter); in s3_pci_remove()
1399 if (par->mmio) in s3_pci_remove()
1400 iounmap(par->mmio); in s3_pci_remove()
1416 struct s3fb_info *par = info->par; in s3_pci_suspend() local
1421 mutex_lock(&(par->open_lock)); in s3_pci_suspend()
1423 if (par->ref_count == 0) { in s3_pci_suspend()
1424 mutex_unlock(&(par->open_lock)); in s3_pci_suspend()
1431 mutex_unlock(&(par->open_lock)); in s3_pci_suspend()
1443 struct s3fb_info *par = info->par; in s3_pci_resume() local
1448 mutex_lock(&(par->open_lock)); in s3_pci_resume()
1450 if (par->ref_count == 0) { in s3_pci_resume()
1451 mutex_unlock(&(par->open_lock)); in s3_pci_resume()
1459 mutex_unlock(&(par->open_lock)); in s3_pci_resume()