Lines Matching refs:via_write_reg
38 via_write_reg(VIACR, 0x00, raw.hor_total & 0xFF); in via_set_primary_timing()
39 via_write_reg(VIACR, 0x01, raw.hor_addr & 0xFF); in via_set_primary_timing()
40 via_write_reg(VIACR, 0x02, raw.hor_blank_start & 0xFF); in via_set_primary_timing()
42 via_write_reg(VIACR, 0x04, raw.hor_sync_start & 0xFF); in via_set_primary_timing()
45 via_write_reg(VIACR, 0x06, raw.ver_total & 0xFF); in via_set_primary_timing()
55 via_write_reg(VIACR, 0x10, raw.ver_sync_start & 0xFF); in via_set_primary_timing()
57 via_write_reg(VIACR, 0x12, raw.ver_addr & 0xFF); in via_set_primary_timing()
58 via_write_reg(VIACR, 0x15, raw.ver_blank_start & 0xFF); in via_set_primary_timing()
59 via_write_reg(VIACR, 0x16, raw.ver_blank_end & 0xFF); in via_set_primary_timing()
93 via_write_reg(VIACR, 0x50, raw.hor_total & 0xFF); in via_set_secondary_timing()
94 via_write_reg(VIACR, 0x51, raw.hor_addr & 0xFF); in via_set_secondary_timing()
95 via_write_reg(VIACR, 0x52, raw.hor_blank_start & 0xFF); in via_set_secondary_timing()
96 via_write_reg(VIACR, 0x53, raw.hor_blank_end & 0xFF); in via_set_secondary_timing()
97 via_write_reg(VIACR, 0x54, (raw.hor_blank_start >> 8 & 0x07) in via_set_secondary_timing()
102 via_write_reg(VIACR, 0x56, raw.hor_sync_start & 0xFF); in via_set_secondary_timing()
103 via_write_reg(VIACR, 0x57, raw.hor_sync_end & 0xFF); in via_set_secondary_timing()
104 via_write_reg(VIACR, 0x58, raw.ver_total & 0xFF); in via_set_secondary_timing()
105 via_write_reg(VIACR, 0x59, raw.ver_addr & 0xFF); in via_set_secondary_timing()
106 via_write_reg(VIACR, 0x5A, raw.ver_blank_start & 0xFF); in via_set_secondary_timing()
107 via_write_reg(VIACR, 0x5B, raw.ver_blank_end & 0xFF); in via_set_secondary_timing()
108 via_write_reg(VIACR, 0x5C, (raw.ver_blank_start >> 8 & 0x07) in via_set_secondary_timing()
112 via_write_reg(VIACR, 0x5D, (raw.ver_total >> 8 & 0x07) in via_set_secondary_timing()
116 via_write_reg(VIACR, 0x5E, raw.ver_sync_start & 0xFF); in via_set_secondary_timing()
117 via_write_reg(VIACR, 0x5F, (raw.ver_sync_end & 0x1F) in via_set_secondary_timing()
124 via_write_reg(VIACR, 0x0D, addr & 0xFF); in via_set_primary_address()
125 via_write_reg(VIACR, 0x0C, (addr >> 8) & 0xFF); in via_set_primary_address()
126 via_write_reg(VIACR, 0x34, (addr >> 16) & 0xFF); in via_set_primary_address()
135 via_write_reg(VIACR, 0x63, (addr >> 10) & 0xFF); in via_set_secondary_address()
136 via_write_reg(VIACR, 0x64, (addr >> 18) & 0xFF); in via_set_secondary_address()
147 via_write_reg(VIACR, 0x13, pitch & 0xFF); in via_set_primary_pitch()
155 via_write_reg(VIACR, 0x66, pitch & 0xFF); in via_set_secondary_pitch()