Lines Matching refs:bridge
55 static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge) in ca91cx42_DMA_irqhandler() argument
57 wake_up(&bridge->dma_queue); in ca91cx42_DMA_irqhandler()
62 static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat) in ca91cx42_LM_irqhandler() argument
70 bridge->lm_callback[i](bridge->lm_data[i]); in ca91cx42_LM_irqhandler()
79 static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask) in ca91cx42_MB_irqhandler() argument
81 wake_up(&bridge->mbox_queue); in ca91cx42_MB_irqhandler()
86 static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge) in ca91cx42_IACK_irqhandler() argument
88 wake_up(&bridge->iack_queue); in ca91cx42_IACK_irqhandler()
96 struct ca91cx42_driver *bridge; in ca91cx42_VERR_irqhandler() local
98 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_VERR_irqhandler()
100 val = ioread32(bridge->base + DGCS); in ca91cx42_VERR_irqhandler()
113 struct ca91cx42_driver *bridge; in ca91cx42_LERR_irqhandler() local
115 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_LERR_irqhandler()
117 val = ioread32(bridge->base + DGCS); in ca91cx42_LERR_irqhandler()
131 struct ca91cx42_driver *bridge; in ca91cx42_VIRQ_irqhandler() local
133 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_VIRQ_irqhandler()
138 vec = ioread32(bridge->base + in ca91cx42_VIRQ_irqhandler()
154 struct ca91cx42_driver *bridge; in ca91cx42_irqhandler() local
158 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_irqhandler()
160 enable = ioread32(bridge->base + LINT_EN); in ca91cx42_irqhandler()
161 stat = ioread32(bridge->base + LINT_STAT); in ca91cx42_irqhandler()
170 serviced |= ca91cx42_DMA_irqhandler(bridge); in ca91cx42_irqhandler()
173 serviced |= ca91cx42_LM_irqhandler(bridge, stat); in ca91cx42_irqhandler()
175 serviced |= ca91cx42_MB_irqhandler(bridge, stat); in ca91cx42_irqhandler()
177 serviced |= ca91cx42_IACK_irqhandler(bridge); in ca91cx42_irqhandler()
189 iowrite32(serviced, bridge->base + LINT_STAT); in ca91cx42_irqhandler()
198 struct ca91cx42_driver *bridge; in ca91cx42_irq_init() local
200 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_irq_init()
206 iowrite32(0, bridge->base + VINT_EN); in ca91cx42_irq_init()
209 iowrite32(0, bridge->base + LINT_EN); in ca91cx42_irq_init()
211 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); in ca91cx42_irq_init()
222 iowrite32(0, bridge->base + LINT_MAP0); in ca91cx42_irq_init()
223 iowrite32(0, bridge->base + LINT_MAP1); in ca91cx42_irq_init()
224 iowrite32(0, bridge->base + LINT_MAP2); in ca91cx42_irq_init()
231 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_irq_init()
236 static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge, in ca91cx42_irq_exit() argument
242 iowrite32(0, bridge->base + VINT_EN); in ca91cx42_irq_exit()
245 iowrite32(0, bridge->base + LINT_EN); in ca91cx42_irq_exit()
247 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); in ca91cx42_irq_exit()
249 ca91cx42_bridge = container_of((void *)bridge, struct vme_bridge, in ca91cx42_irq_exit()
254 static int ca91cx42_iack_received(struct ca91cx42_driver *bridge, int level) in ca91cx42_iack_received() argument
258 tmp = ioread32(bridge->base + LINT_STAT); in ca91cx42_iack_received()
275 struct ca91cx42_driver *bridge; in ca91cx42_irq_set() local
277 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_irq_set()
280 tmp = ioread32(bridge->base + LINT_EN); in ca91cx42_irq_set()
287 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_irq_set()
300 struct ca91cx42_driver *bridge; in ca91cx42_irq_generate() local
302 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_irq_generate()
308 mutex_lock(&bridge->vme_int); in ca91cx42_irq_generate()
310 tmp = ioread32(bridge->base + VINT_EN); in ca91cx42_irq_generate()
313 iowrite32(statid << 24, bridge->base + STATID); in ca91cx42_irq_generate()
317 iowrite32(tmp, bridge->base + VINT_EN); in ca91cx42_irq_generate()
320 wait_event_interruptible(bridge->iack_queue, in ca91cx42_irq_generate()
321 ca91cx42_iack_received(bridge, level)); in ca91cx42_irq_generate()
324 tmp = ioread32(bridge->base + VINT_EN); in ca91cx42_irq_generate()
326 iowrite32(tmp, bridge->base + VINT_EN); in ca91cx42_irq_generate()
328 mutex_unlock(&bridge->vme_int); in ca91cx42_irq_generate()
341 struct ca91cx42_driver *bridge; in ca91cx42_slave_set() local
345 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_slave_set()
404 temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
406 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
409 iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]); in ca91cx42_slave_set()
410 iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]); in ca91cx42_slave_set()
411 iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]); in ca91cx42_slave_set()
429 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
434 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
445 struct ca91cx42_driver *bridge; in ca91cx42_slave_get() local
447 bridge = image->parent->driver_priv; in ca91cx42_slave_get()
457 ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_get()
459 *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]); in ca91cx42_slave_get()
460 vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]); in ca91cx42_slave_get()
461 pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]); in ca91cx42_slave_get()
598 struct ca91cx42_driver *bridge; in ca91cx42_master_set() local
602 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_master_set()
650 temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
652 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
723 iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]); in ca91cx42_master_set()
724 iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]); in ca91cx42_master_set()
725 iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]); in ca91cx42_master_set()
728 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
733 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
752 struct ca91cx42_driver *bridge; in __ca91cx42_master_get() local
754 bridge = image->parent->driver_priv; in __ca91cx42_master_get()
758 ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); in __ca91cx42_master_get()
760 pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]); in __ca91cx42_master_get()
761 vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]); in __ca91cx42_master_get()
762 pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]); in __ca91cx42_master_get()
969 struct ca91cx42_driver *bridge; in ca91cx42_master_rmw() local
972 bridge = image->parent->driver_priv; in ca91cx42_master_rmw()
978 mutex_lock(&bridge->vme_rmw); in ca91cx42_master_rmw()
993 iowrite32(0, bridge->base + SCYC_CTL); in ca91cx42_master_rmw()
996 iowrite32(mask, bridge->base + SCYC_EN); in ca91cx42_master_rmw()
997 iowrite32(compare, bridge->base + SCYC_CMP); in ca91cx42_master_rmw()
998 iowrite32(swap, bridge->base + SCYC_SWP); in ca91cx42_master_rmw()
999 iowrite32(pci_addr, bridge->base + SCYC_ADDR); in ca91cx42_master_rmw()
1002 iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL); in ca91cx42_master_rmw()
1008 iowrite32(0, bridge->base + SCYC_CTL); in ca91cx42_master_rmw()
1013 mutex_unlock(&bridge->vme_rmw); in ca91cx42_master_rmw()
1165 struct ca91cx42_driver *bridge; in ca91cx42_dma_busy() local
1167 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_dma_busy()
1169 tmp = ioread32(bridge->base + DGCS); in ca91cx42_dma_busy()
1185 struct ca91cx42_driver *bridge; in ca91cx42_dma_list_exec() local
1189 bridge = ctrlr->parent->driver_priv; in ca91cx42_dma_list_exec()
1215 iowrite32(0, bridge->base + DTBC); in ca91cx42_dma_list_exec()
1216 iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP); in ca91cx42_dma_list_exec()
1219 val = ioread32(bridge->base + DGCS); in ca91cx42_dma_list_exec()
1228 iowrite32(val, bridge->base + DGCS); in ca91cx42_dma_list_exec()
1232 iowrite32(val, bridge->base + DGCS); in ca91cx42_dma_list_exec()
1234 retval = wait_event_interruptible(bridge->dma_queue, in ca91cx42_dma_list_exec()
1238 val = ioread32(bridge->base + DGCS); in ca91cx42_dma_list_exec()
1239 iowrite32(val | CA91CX42_DGCS_STOP_REQ, bridge->base + DGCS); in ca91cx42_dma_list_exec()
1241 wait_event(bridge->dma_queue, in ca91cx42_dma_list_exec()
1251 val = ioread32(bridge->base + DGCS); in ca91cx42_dma_list_exec()
1257 val = ioread32(bridge->base + DCTL); in ca91cx42_dma_list_exec()
1298 struct ca91cx42_driver *bridge; in ca91cx42_lm_set() local
1301 bridge = lm->parent->driver_priv; in ca91cx42_lm_set()
1316 if (bridge->lm_callback[i]) { in ca91cx42_lm_set()
1350 iowrite32(lm_base, bridge->base + LM_BS); in ca91cx42_lm_set()
1351 iowrite32(lm_ctl, bridge->base + LM_CTL); in ca91cx42_lm_set()
1365 struct ca91cx42_driver *bridge; in ca91cx42_lm_get() local
1367 bridge = lm->parent->driver_priv; in ca91cx42_lm_get()
1371 *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS); in ca91cx42_lm_get()
1372 lm_ctl = ioread32(bridge->base + LM_CTL); in ca91cx42_lm_get()
1408 struct ca91cx42_driver *bridge; in ca91cx42_lm_attach() local
1411 bridge = lm->parent->driver_priv; in ca91cx42_lm_attach()
1417 lm_ctl = ioread32(bridge->base + LM_CTL); in ca91cx42_lm_attach()
1425 if (bridge->lm_callback[monitor]) { in ca91cx42_lm_attach()
1432 bridge->lm_callback[monitor] = callback; in ca91cx42_lm_attach()
1433 bridge->lm_data[monitor] = data; in ca91cx42_lm_attach()
1436 tmp = ioread32(bridge->base + LINT_EN); in ca91cx42_lm_attach()
1438 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_lm_attach()
1443 iowrite32(lm_ctl, bridge->base + LM_CTL); in ca91cx42_lm_attach()
1457 struct ca91cx42_driver *bridge; in ca91cx42_lm_detach() local
1459 bridge = lm->parent->driver_priv; in ca91cx42_lm_detach()
1464 tmp = ioread32(bridge->base + LINT_EN); in ca91cx42_lm_detach()
1466 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_lm_detach()
1469 bridge->base + LINT_STAT); in ca91cx42_lm_detach()
1472 bridge->lm_callback[monitor] = NULL; in ca91cx42_lm_detach()
1473 bridge->lm_data[monitor] = NULL; in ca91cx42_lm_detach()
1478 tmp = ioread32(bridge->base + LM_CTL); in ca91cx42_lm_detach()
1480 iowrite32(tmp, bridge->base + LM_CTL); in ca91cx42_lm_detach()
1491 struct ca91cx42_driver *bridge; in ca91cx42_slot_get() local
1493 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_slot_get()
1496 slot = ioread32(bridge->base + VCSR_BS); in ca91cx42_slot_get()
1540 struct ca91cx42_driver *bridge; in ca91cx42_crcsr_init() local
1542 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_crcsr_init()
1548 iowrite32(geoid << 27, bridge->base + VCSR_BS); in ca91cx42_crcsr_init()
1558 bridge->crcsr_kernel = dma_alloc_coherent(&pdev->dev, in ca91cx42_crcsr_init()
1560 &bridge->crcsr_bus, GFP_KERNEL); in ca91cx42_crcsr_init()
1561 if (!bridge->crcsr_kernel) { in ca91cx42_crcsr_init()
1568 iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO); in ca91cx42_crcsr_init()
1570 tmp = ioread32(bridge->base + VCSR_CTL); in ca91cx42_crcsr_init()
1572 iowrite32(tmp, bridge->base + VCSR_CTL); in ca91cx42_crcsr_init()
1581 struct ca91cx42_driver *bridge; in ca91cx42_crcsr_exit() local
1583 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_crcsr_exit()
1586 tmp = ioread32(bridge->base + VCSR_CTL); in ca91cx42_crcsr_exit()
1588 iowrite32(tmp, bridge->base + VCSR_CTL); in ca91cx42_crcsr_exit()
1591 iowrite32(0, bridge->base + VCSR_TO); in ca91cx42_crcsr_exit()
1594 bridge->crcsr_kernel, bridge->crcsr_bus); in ca91cx42_crcsr_exit()
1851 struct ca91cx42_driver *bridge; in ca91cx42_remove() local
1854 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_remove()
1858 iowrite32(0, bridge->base + LINT_EN); in ca91cx42_remove()
1861 iowrite32(0x00800000, bridge->base + LSI0_CTL); in ca91cx42_remove()
1862 iowrite32(0x00800000, bridge->base + LSI1_CTL); in ca91cx42_remove()
1863 iowrite32(0x00800000, bridge->base + LSI2_CTL); in ca91cx42_remove()
1864 iowrite32(0x00800000, bridge->base + LSI3_CTL); in ca91cx42_remove()
1865 iowrite32(0x00800000, bridge->base + LSI4_CTL); in ca91cx42_remove()
1866 iowrite32(0x00800000, bridge->base + LSI5_CTL); in ca91cx42_remove()
1867 iowrite32(0x00800000, bridge->base + LSI6_CTL); in ca91cx42_remove()
1868 iowrite32(0x00800000, bridge->base + LSI7_CTL); in ca91cx42_remove()
1869 iowrite32(0x00F00000, bridge->base + VSI0_CTL); in ca91cx42_remove()
1870 iowrite32(0x00F00000, bridge->base + VSI1_CTL); in ca91cx42_remove()
1871 iowrite32(0x00F00000, bridge->base + VSI2_CTL); in ca91cx42_remove()
1872 iowrite32(0x00F00000, bridge->base + VSI3_CTL); in ca91cx42_remove()
1873 iowrite32(0x00F00000, bridge->base + VSI4_CTL); in ca91cx42_remove()
1874 iowrite32(0x00F00000, bridge->base + VSI5_CTL); in ca91cx42_remove()
1875 iowrite32(0x00F00000, bridge->base + VSI6_CTL); in ca91cx42_remove()
1876 iowrite32(0x00F00000, bridge->base + VSI7_CTL); in ca91cx42_remove()
1911 ca91cx42_irq_exit(bridge, pdev); in ca91cx42_remove()
1913 iounmap(bridge->base); in ca91cx42_remove()