Lines Matching refs:ioread32be
127 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); in tsi148_MB_irqhandler()
148 ioread32be(bridge->base + TSI148_LCSR_EDPAU), in tsi148_PERR_irqhandler()
149 ioread32be(bridge->base + TSI148_LCSR_EDPAL), in tsi148_PERR_irqhandler()
150 ioread32be(bridge->base + TSI148_LCSR_EDPAT)); in tsi148_PERR_irqhandler()
154 ioread32be(bridge->base + TSI148_LCSR_EDPXA), in tsi148_PERR_irqhandler()
155 ioread32be(bridge->base + TSI148_LCSR_EDPXS)); in tsi148_PERR_irqhandler()
175 error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU); in tsi148_VERR_irqhandler()
176 error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL); in tsi148_VERR_irqhandler()
177 error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT); in tsi148_VERR_irqhandler()
255 enable = ioread32be(bridge->base + TSI148_LCSR_INTEO); in tsi148_irqhandler()
256 stat = ioread32be(bridge->base + TSI148_LCSR_INTS); in tsi148_irqhandler()
388 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); in tsi148_iack_received()
410 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); in tsi148_irq_set()
414 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); in tsi148_irq_set()
423 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); in tsi148_irq_set()
427 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); in tsi148_irq_set()
448 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); in tsi148_irq_generate()
538 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
631 ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
634 vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
636 vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
638 vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
640 vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
642 pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
644 pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
902 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
1063 ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1066 pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1068 pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1070 pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1072 pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1074 vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1076 vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1382 pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_rmw()
1384 pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_rmw()
1398 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); in tsi148_master_rmw()
1403 result = ioread32be(image->kern_base + offset); in tsi148_master_rmw()
1406 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); in tsi148_master_rmw()
1786 tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + in tsi148_dma_busy()
1847 dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + in tsi148_dma_list_exec()
1871 val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + in tsi148_dma_list_exec()
1996 lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU); in tsi148_lm_get()
1997 lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL); in tsi148_lm_get()
1998 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); in tsi148_lm_get()
2051 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); in tsi148_lm_attach()
2071 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); in tsi148_lm_attach()
2075 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); in tsi148_lm_attach()
2103 lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN); in tsi148_lm_detach()
2107 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); in tsi148_lm_detach()
2121 tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT); in tsi148_lm_detach()
2142 slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT); in tsi148_slot_get()
2210 cbar = ioread32be(bridge->base + TSI148_CBAR); in tsi148_crcsr_init()
2222 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); in tsi148_crcsr_init()
2257 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); in tsi148_crcsr_exit()
2473 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT); in tsi148_probe()
2501 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT); in tsi148_probe()
2604 if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800) in tsi148_remove()