Lines Matching defs:drm_amdgpu_info_device
975 struct drm_amdgpu_info_device { struct
977 __u32 device_id;
979 __u32 chip_rev;
980 __u32 external_rev;
982 __u32 pci_rev;
983 __u32 family;
984 __u32 num_shader_engines;
985 __u32 num_shader_arrays_per_engine;
987 __u32 gpu_counter_freq;
988 __u64 max_engine_clock;
989 __u64 max_memory_clock;
991 __u32 cu_active_number;
993 __u32 cu_ao_mask;
994 __u32 cu_bitmap[4][4];
996 __u32 enabled_rb_pipes_mask;
997 __u32 num_rb_pipes;
998 __u32 num_hw_gfx_contexts;
999 __u32 _pad;
1000 __u64 ids_flags;
1002 __u64 virtual_address_offset;
1004 __u64 virtual_address_max;
1006 __u32 virtual_address_alignment;
1008 __u32 pte_fragment_size;
1009 __u32 gart_page_size;
1011 __u32 ce_ram_size;
1013 __u32 vram_type;
1015 __u32 vram_bit_width;
1017 __u32 vce_harvest_config;
1019 __u32 gc_double_offchip_lds_buf;
1021 __u64 prim_buf_gpu_addr;
1023 __u64 pos_buf_gpu_addr;
1025 __u64 cntl_sb_buf_gpu_addr;
1027 __u64 param_buf_gpu_addr;
1028 __u32 prim_buf_size;
1029 __u32 pos_buf_size;
1030 __u32 cntl_sb_buf_size;
1031 __u32 param_buf_size;
1033 __u32 wave_front_size;
1035 __u32 num_shader_visible_vgprs;
1037 __u32 num_cu_per_sh;
1039 __u32 num_tcc_blocks;
1041 __u32 gs_vgt_table_depth;
1043 __u32 gs_prim_buffer_depth;
1045 __u32 max_gs_waves_per_vgt;
1046 __u32 _pad1;
1048 __u32 cu_ao_bitmap[4][4];
1050 __u64 high_va_offset;
1052 __u64 high_va_max;
1054 __u32 pa_sc_tile_steering_override;
1056 __u64 tcc_disabled_mask;