Lines Matching refs:HDA_DSP_HDA_BAR
45 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL, in hda_dsp_ctrl_link_reset()
51 gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL); in hda_dsp_ctrl_link_reset()
81 offset = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_LLCH); in hda_dsp_ctrl_get_caps()
87 cap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, offset); in hda_dsp_ctrl_get_caps()
175 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2, in hda_dsp_ctrl_clock_power_gating()
249 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, in hda_dsp_ctrl_init_chip()
255 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS, in hda_dsp_ctrl_init_chip()
264 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS, in hda_dsp_ctrl_init_chip()
273 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, in hda_dsp_ctrl_init_chip()
279 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE, in hda_dsp_ctrl_init_chip()
281 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE, in hda_dsp_ctrl_init_chip()
314 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, in hda_dsp_ctrl_stop_chip()
322 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, in hda_dsp_ctrl_stop_chip()
326 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, in hda_dsp_ctrl_stop_chip()
333 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, in hda_dsp_ctrl_stop_chip()
339 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS, in hda_dsp_ctrl_stop_chip()
348 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS, in hda_dsp_ctrl_stop_chip()
357 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, in hda_dsp_ctrl_stop_chip()
359 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, in hda_dsp_ctrl_stop_chip()