Lines Matching refs:writel
141 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx()
169 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx()
208 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
211 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
226 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
258 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk()
265 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
295 writel(reg_val_MCR | (mcfg->tx_multichannel_enable ? in configure_multichannel()
298 writel(mcfg->tx_channel_0_enable, in configure_multichannel()
300 writel(mcfg->tx_channel_1_enable, in configure_multichannel()
302 writel(mcfg->tx_channel_2_enable, in configure_multichannel()
304 writel(mcfg->tx_channel_3_enable, in configure_multichannel()
316 writel(reg_val_MCR | (mcfg->rx_multichannel_enable ? in configure_multichannel()
319 writel(mcfg->rx_channel_0_enable, in configure_multichannel()
321 writel(mcfg->rx_channel_1_enable, in configure_multichannel()
323 writel(mcfg->rx_channel_2_enable, in configure_multichannel()
325 writel(mcfg->rx_channel_3_enable, in configure_multichannel()
335 writel(reg_val_MCR | in configure_multichannel()
339 writel(mcfg->comparison_mask, in configure_multichannel()
341 writel(mcfg->comparison_value, in configure_multichannel()
385 writel(reg_val_DMACR, msp->registers + MSP_DMACR); in enable_msp()
387 writel(config->iodelay, msp->registers + MSP_IODLY); in enable_msp()
391 writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR); in enable_msp()
402 writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR); in flush_fifo_rx()
410 writel(reg_val_GCR, msp->registers + MSP_GCR); in flush_fifo_rx()
419 writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR); in flush_fifo_tx()
420 writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR); in flush_fifo_tx()
427 writel(0x0, msp->registers + MSP_ITCR); in flush_fifo_tx()
428 writel(reg_val_GCR, msp->registers + MSP_GCR); in flush_fifo_tx()
482 writel(new_reg, msp->registers + MSP_GCR); in ux500_msp_i2s_open()
506 writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR); in disable_msp_rx()
508 writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR); in disable_msp_rx()
510 writel(reg_val_IMSC & in disable_msp_rx()
522 writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR); in disable_msp_tx()
524 writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR); in disable_msp_tx()
526 writel(reg_val_IMSC & in disable_msp_tx()
543 writel(reg_val_GCR | LOOPBACK_MASK, in disable_msp()
550 writel((readl(msp->registers + MSP_GCR) & in disable_msp()
557 writel((readl(msp->registers + MSP_GCR) & in disable_msp()
590 writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR); in ux500_msp_i2s_trigger()
618 writel((readl(msp->registers + MSP_GCR) & in ux500_msp_i2s_close()
622 writel(0, msp->registers + MSP_GCR); in ux500_msp_i2s_close()
623 writel(0, msp->registers + MSP_TCF); in ux500_msp_i2s_close()
624 writel(0, msp->registers + MSP_RCF); in ux500_msp_i2s_close()
625 writel(0, msp->registers + MSP_DMACR); in ux500_msp_i2s_close()
626 writel(0, msp->registers + MSP_SRG); in ux500_msp_i2s_close()
627 writel(0, msp->registers + MSP_MCR); in ux500_msp_i2s_close()
628 writel(0, msp->registers + MSP_RCM); in ux500_msp_i2s_close()
629 writel(0, msp->registers + MSP_RCV); in ux500_msp_i2s_close()
630 writel(0, msp->registers + MSP_TCE0); in ux500_msp_i2s_close()
631 writel(0, msp->registers + MSP_TCE1); in ux500_msp_i2s_close()
632 writel(0, msp->registers + MSP_TCE2); in ux500_msp_i2s_close()
633 writel(0, msp->registers + MSP_TCE3); in ux500_msp_i2s_close()
634 writel(0, msp->registers + MSP_RCE0); in ux500_msp_i2s_close()
635 writel(0, msp->registers + MSP_RCE1); in ux500_msp_i2s_close()
636 writel(0, msp->registers + MSP_RCE2); in ux500_msp_i2s_close()
637 writel(0, msp->registers + MSP_RCE3); in ux500_msp_i2s_close()