Lines Matching refs:P1
121 P1()
132 CPU and P1() represents the read() routine running on another. The
134 Thus, P0 stores the data in buf and then sets flag. Meanwhile, P1
153 A memory model will predict what values P1 might obtain for its loads
162 instance, P1 might run entirely before P0 begins, in which case r1 and
163 r2 will both be 0 at the end. Or P0 might run entirely before P1
167 routines run concurrently. One possibility is that P1 runs after P0's
169 will again both be 0. (If P1 had been designed to read buf
196 Since r1 = 1, P0 must store 1 to flag before P1 loads 1 from
199 P1 loads from flag before loading from buf, since CPUs execute
202 P1 must load 0 from buf before P0 stores 1 to it; otherwise r2
235 P1()
271 X: P1 loads 1 from flag executes before
272 Y: P1 loads 0 from buf executes before
517 P1()
541 P1()
548 If r1 = 0x56781234 (little-endian!) at the end, then P1 must have read
649 P1()
664 READ_ONCE() in P1, on Itanium it sometimes could end up with r1 = 5
1089 P1()
1098 can malfunction on Alpha systems (notice that P1 uses an ordinary load
1103 smp_wmb() forces P0's store to x to propagate to P1 before the store
1104 to ptr does. And since P1 can't execute its second load
1106 first load, the value x = 1 must have propagated to P1 before the
1110 stores do reach P1's local cache in the proper order, it can happen
1113 value may not become available for P1's CPU to read until after the
1123 between P1's two loads when the kernel is compiled for the Alpha
1130 P1()
1139 then we would never get r1 = &x and r2 = 0. By the time P1 executed
1211 P1()
1221 event, because P1's store came after P0's store in x's coherence
1222 order, and P1's store propagated to P0 before P0's load executed.
1237 P1()
1247 because P1's store overwrote the value read by P0's first load, and
1248 P1's store propagated to P0 before P0's second load executed.
1263 P1()
1274 from P1's second load to its first (backwards!). The reason is
1275 similar to the previous examples: The value P1 loads from buf gets
1277 to buf will propagate to P1 before the store to flag does, and the
1278 store to flag propagates to P1 before P1 reads flag.
1281 P1 must execute its second load before the first. Indeed, if the load
1283 have propagated to P1 by the time P1's load from buf executed, so r2
1288 But what if we put an smp_rmb() fence between P1's loads? The fence
1315 P1()
1332 overwritten by P1's store since x = 2 at the end (a coe link), the
1333 smp_wmb() ensures that P1's store to x propagates to P2 before the
1403 P1()
1412 If r0 = 0 at the end then there is a pb link from P0's load to P1's
1413 load: an fre link from P0's load to P1's store (which overwrites the
1414 value read by P0), and a strong fence between P1's store and its load.
1419 Similarly, if r1 = 0 at the end then there is a pb link from P1's load
1472 P1()
1483 means that P0's store to x propagated to P1 before P1 called
1485 P1's grace period, contrary to part (2) of the Guarantee. On the
1487 end of the critical section, did not propagate to P1 before the end of
1682 P1()
1693 P1's load at W reads from, so we have W ->fre Y. Since S ->po W and
1697 If r1 = 1 at the end then P1's load at Z reads from P0's store at X,
1720 P1()
1747 P0 P1 P2
1765 section in P0 both starts before P1's grace period does and ends
1766 before it does, and the critical section in P2 both starts after P1's
1838 P1()
1890 P1()
1909 If r1 = 1 at the end then the spin_lock() in P1 must have read from
1951 P1()
1958 P1's store to x propagates to P0 before P0's load from x executes.
1974 NULL pointer, because P1's store to x might propagate to P0 after the
2086 P1()
2098 means that the store to buf must propagate from P0 to P1 before Z
2167 P1()
2188 at the machine level, must propagate to P1 before X's store to
2192 Y is a valid indicator that X propagated to P1 before Y
2197 The smp_rmb() fence in P1 is a compiler barrier as well as a
2203 Thus U's store to buf is forced to propagate to P1 before V's load
2284 P1()
2302 stores will propagate to P1 in that order. However, rcu_dereference()
2305 that the load of ptr in P1 is r-pre-bounded before the load of *p
2350 P1()
2358 Do the plain stores to y race? Clearly not if P1 reads a non-zero
2360 means that the read-side critical section in P1 must finish executing
2363 P1 before the critical section started and so would have been visible
2368 This means there is an rcu-fence link from P1's "y = 2" store to P0's
2369 "y = 3" store, and consequently the first must propagate from P1 to P0
2371 concurrent and there is no race, even though P1's plain store to y
2547 P1()
2558 you it is not, but the model won't mention that this is because P1