Lines Matching refs:rdmsr
144 cr0 &= rdmsr(MSR_IA32_VMX_CR0_FIXED1); in prepare_for_vmx_operation()
145 cr0 |= rdmsr(MSR_IA32_VMX_CR0_FIXED0); in prepare_for_vmx_operation()
149 cr4 &= rdmsr(MSR_IA32_VMX_CR4_FIXED1); in prepare_for_vmx_operation()
150 cr4 |= rdmsr(MSR_IA32_VMX_CR4_FIXED0); in prepare_for_vmx_operation()
163 feature_control = rdmsr(MSR_IA32_FEAT_CTL); in prepare_for_vmx_operation()
211 vmwrite(PIN_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PINBASED_CTLS)); in init_vmcs_control_fields()
218 .ad_enabled = !!(rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & VMX_EPT_VPID_CAP_AD_BITS), in init_vmcs_control_fields()
229 rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS) | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); in init_vmcs_control_fields()
231 vmwrite(CPU_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS)); in init_vmcs_control_fields()
239 vmwrite(VM_EXIT_CONTROLS, rdmsr(MSR_IA32_VMX_EXIT_CTLS) | in init_vmcs_control_fields()
243 vmwrite(VM_ENTRY_CONTROLS, rdmsr(MSR_IA32_VMX_ENTRY_CTLS) | in init_vmcs_control_fields()
277 vmwrite(HOST_IA32_PAT, rdmsr(MSR_IA32_CR_PAT)); in init_vmcs_host_state()
279 vmwrite(HOST_IA32_EFER, rdmsr(MSR_EFER)); in init_vmcs_host_state()
282 rdmsr(MSR_CORE_PERF_GLOBAL_CTRL)); in init_vmcs_host_state()
284 vmwrite(HOST_IA32_SYSENTER_CS, rdmsr(MSR_IA32_SYSENTER_CS)); in init_vmcs_host_state()
289 vmwrite(HOST_FS_BASE, rdmsr(MSR_FS_BASE)); in init_vmcs_host_state()
290 vmwrite(HOST_GS_BASE, rdmsr(MSR_GS_BASE)); in init_vmcs_host_state()
295 vmwrite(HOST_IA32_SYSENTER_ESP, rdmsr(MSR_IA32_SYSENTER_ESP)); in init_vmcs_host_state()
296 vmwrite(HOST_IA32_SYSENTER_EIP, rdmsr(MSR_IA32_SYSENTER_EIP)); in init_vmcs_host_state()