Lines Matching refs:attr
634 const uint32_t attr = TEE_MATTR_VALID_BLOCK; in core_mmu_type_to_attr() local
641 return attr | TEE_MATTR_SECURE | TEE_MATTR_PRWX | cached; in core_mmu_type_to_attr()
645 return attr | TEE_MATTR_SECURE | TEE_MATTR_PRX | cached; in core_mmu_type_to_attr()
648 return attr | TEE_MATTR_SECURE | TEE_MATTR_PR | cached; in core_mmu_type_to_attr()
653 return attr | TEE_MATTR_SECURE | TEE_MATTR_PRW | cached; in core_mmu_type_to_attr()
655 return attr | TEE_MATTR_SECURE | TEE_MATTR_PRWX | noncache; in core_mmu_type_to_attr()
657 return attr | TEE_MATTR_SECURE | TEE_MATTR_PRW | cached; in core_mmu_type_to_attr()
659 return attr | TEE_MATTR_PRW | cached; in core_mmu_type_to_attr()
662 return attr | TEE_MATTR_PRW | noncache; in core_mmu_type_to_attr()
664 return attr | TEE_MATTR_SECURE | TEE_MATTR_PRW | noncache; in core_mmu_type_to_attr()
666 return attr | TEE_MATTR_PRW | cached; in core_mmu_type_to_attr()
669 return attr | TEE_MATTR_SECURE | TEE_MATTR_PRW | cached; in core_mmu_type_to_attr()
740 uint32_t attr; in dump_xlat_table() local
745 core_mmu_get_entry(&tbl_info, idx, &pa, &attr); in dump_xlat_table()
746 if (attr || level > CORE_MMU_BASE_TABLE_LEVEL) { in dump_xlat_table()
747 if (attr & TEE_MATTR_TABLE) { in dump_xlat_table()
756 attr & TEE_MATTR_SECURE ? " S" : "NS"); in dump_xlat_table()
759 } else if (attr) { in dump_xlat_table()
763 attr & (TEE_MATTR_CACHE_CACHED << in dump_xlat_table()
765 attr & TEE_MATTR_PW ? "RW" : "RO", in dump_xlat_table()
766 attr & TEE_MATTR_PX ? "X " : "XN", in dump_xlat_table()
767 attr & TEE_MATTR_SECURE ? " S" : "NS"); in dump_xlat_table()
830 mmap[pos].attr = core_mmu_type_to_attr(MEM_AREA_PAGER_VASPACE); in add_pager_vaspace()
969 map->attr = core_mmu_type_to_attr(map->type); in assign_mem_va()
1000 map->attr = core_mmu_type_to_attr(map->type); in assign_mem_va()
1087 .attr = core_mmu_type_to_attr(MEM_AREA_IDENTITY_MAP_RX), in mem_map_add_id_map()
1252 .attr = core_mmu_type_to_attr(MEM_AREA_IDENTITY_MAP_RX), in core_init_mmu_map()
1288 bool core_pbuf_is(uint32_t attr, paddr_t pbuf, size_t len) in core_pbuf_is() argument
1296 switch (attr) { in core_pbuf_is()
1319 return map->attr >> TEE_MATTR_CACHE_SHIFT == in core_pbuf_is()
1327 bool core_vbuf_is(uint32_t attr, const void *vbuf, size_t len) in core_vbuf_is() argument
1339 return core_pbuf_is(attr, p, len); in core_vbuf_is()
1500 paddr_t pa, uint32_t attr) in core_mmu_set_entry() argument
1504 idx, pa, attr); in core_mmu_set_entry()
1508 paddr_t *pa, uint32_t *attr) in core_mmu_get_entry() argument
1512 idx, pa, attr); in core_mmu_get_entry()
1552 core_mmu_set_entry(tbl_info, idx, pa, region->attr); in set_region()
1565 .attr = region->attr, in set_pg_region()
1568 uint32_t pgt_attr = (r.attr & TEE_MATTR_SECURE) | TEE_MATTR_TABLE; in set_pg_region()
1689 idx, mm->attr & TEE_MATTR_SECURE)) in core_mmu_map_region()
1700 core_mmu_set_entry(&tbl_info, idx, paddr, mm->attr); in core_mmu_map_region()
2059 map->attr = core_mmu_type_to_attr(type); in core_mmu_add_mapping()