Lines Matching refs:interrupt
26 interrupt routing model, TF-A appropriately sets the ``FIQ`` and ``IRQ`` bits of
91 Arm GIC architecture defines it, although it's applied to non-interrupt
109 this is implicit when an interrupt is targeted and acknowledged at EL3, and the
110 priority of the acknowledged interrupt is used to match its registered handler.
111 The priority level is likewise implicitly deactivated when the interrupt
112 handling concludes by EOIing the interrupt.
114 Non-interrupt exceptions (SErrors, for example) don't have a notion of priority.
116 for these non-interrupt exceptions to assume a priority, and to interwork with
121 Because priority activation and deactivation for interrupt handling is implicit
123 interrupt to preempt a higher priority one. By extension, this means that a
125 activation and deactivation for non-interrupt exceptions, however, has to be
167 interrupts can then *own* one or more priority levels, and register interrupt
171 Dispatchers are assigned interrupt priority levels in two steps:
201 The priority thus assigned to an interrupt is also used to determine the
238 interrupt properties (as opposed to just numbers) of Secure interrupts. The
272 The interrupt handler should have the following signature:
279 The parameters are as obtained from the top-level :ref:`EL3 interrupt handler
302 * This platform uses 2 bits for interrupt association. In total, 3 upper
331 /* List interrupt properties for GIC driver. All interrupts target EL3 */
367 being handled: for interrupts, this is implied when the interrupt is
368 acknowledged; for non-interrupt exceptions, such as SErrors or :ref:`SDEI
374 above, for interrupts, this is implied when the interrupt is EOId in the GIC;
388 through an ``ERET``, resumes execution before the interrupt occurred.
409 deactivating interrupt:
473 A pending Non-secure interrupt can preempt Secure execution handling a
480 #. A Non-secure interrupt preempts Secure execution. Non-secure interrupt is
515 #. Platform provides interrupt properties to GIC driver, as described in
519 interrupt handler.
531 interrupt properties (see `Programming priority`_), and configures the
535 #. The |EHF|, during its initialisation, registers a top-level interrupt handler
539 #. When an interrupt belonging to a dispatcher fires, GIC raises an EL3/Group 0
540 interrupt, and is taken to EL3.
542 #. The top-level EL3 interrupt handler executes. The handler acknowledges the
543 interrupt, reads its *Running Priority*, and from that, determines the
547 the interrupt received.
556 .. _non-interrupt-flow:
559 interrupt:
585 GIC, interrupt delivery to the PE is subject to GIC prioritisation rules. In
586 particular, when an interrupt is being handled by the PE (i.e., the interrupt is