Lines Matching refs:to
22 is read to determine the priority of the interrupt.
34 associated to system-wide peripherals, and these interrupts can target any PE in
47 associated with peripherals that are private to each PE. Interrupts from private
48 peripherals target to that PE only.
75 the GIC *Set Active Register* to read and return the active status of the
87 ``id``. PEs in the system are expected to receive only enabled interrupts.
90 inserts barrier to make memory updates visible before enabling interrupt, and
91 then writes to GIC *Set Enable Register* to enable the interrupt.
102 ``id``. PEs in the system are not expected to receive disabled interrupts.
105 writes to GIC *Clear Enable Register* to disable the interrupt, and inserts
106 barrier to make memory updates visible afterwards.
118 ``id`` to the value set by the second parameter ``priority``.
121 writes to GIC *Priority Register* set interrupt priority.
167 This API should set the interrupt specified by first parameter ``id`` to the
171 - ``INTR_TYPE_NS``: interrupt is meant to be consumed by the Non-secure world.
173 - ``INTR_TYPE_S_EL1``: interrupt is meant to be consumed by Secure EL1.
175 - ``INTR_TYPE_EL3``: interrupt is meant to be consumed by EL3.
178 writes to the GIC *Group Register* and *Group Modifier Register* (only GICv3) to
179 assign the interrupt to the right group.
183 - ``INTR_TYPE_NS`` maps to Group 1 interrupt.
185 - ``INTR_TYPE_S_EL1`` maps to Secure Group 1 interrupt.
187 - ``INTR_TYPE_EL3`` maps to Secure Group 0 interrupt.
191 - ``INTR_TYPE_NS`` maps to Group 1 interrupt.
193 - When the build option ``GICV2_G0_FOR_EL3`` is set to ``0`` (the default),
194 ``INTR_TYPE_S_EL1`` maps to Group 0. Otherwise, ``INTR_TYPE_EL3`` maps to
211 inserts barrier to make memory updates visible before raising SGI, then writes
212 to appropriate *SGI Register* in order to raise the EL3 SGI.
225 specified by first parameter ``id`` to that specified by the second parameter
230 - ``INTR_ROUTING_MODE_ANY`` means the interrupt can be routed to any PE in the
233 - ``INTR_ROUTING_MODE_PE`` means the interrupt is routed to the PE whose MPIDR
237 writes to the GIC *Target Register* (GICv2) or *Route Register* (GICv3) to set
248 This API should set the interrupt specified by first parameter ``id`` to
252 inserts barrier to make memory updates visible before setting interrupt pending,
253 and writes to the GIC *Set Pending Register* to set the interrupt pending
268 writes to the GIC *Clear Pending Register* to clear the interrupt pending
269 status, and inserts barrier to make memory updates visible afterwards.
281 may be signalled to the PE. The API should return the current priority value
285 inserts to order memory updates before updating mask, then writes to the GIC
287 potential trigger due to mask update.