Lines Matching refs:coherent
1593 - The coherent memory section (if enabled) must be zero-initialised as well.
1594 - The MMU setup code needs to know the extents of the coherent and read-only
2009 Use of coherent memory in TF-A
2018 TF-A defines coherent memory as a region of memory with Device nGnRE attributes
2020 is the smallest possible size of the coherent memory region.
2023 mismatched attributes from various CPUs are allocated in a coherent memory
2024 region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory
2036 Disabling the use of coherent memory in TF-A
2039 It might be desirable to avoid the cost of allocating coherent memory on
2040 platforms which are memory constrained. TF-A enables inclusion of coherent
2045 The below sections analyze the data structures allocated in the coherent memory
2053 structure is allocated in the coherent memory region in TF-A because it can be
2088 them from coherent memory involves only doing a clean and invalidate of the
2099 The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory
2124 cache maintenance is not enough to allocate them in coherent memory. Consider
2209 Non Functional Impact of removing coherent memory
2212 Removal of the coherent memory region leads to the additional software overhead
2231 whether coherent memory should be used. If a platform disables