Lines Matching refs:group
569 This mask reflects the set of group counters that should be enabled. The
570 maximum number of group 1 counters supported by AMUv1 is 16 so the mask
571 can be at most 0xffff. If the platform does not define this mask, no group 1
2111 *power domain*. A *power domain* is a CPU or a logical group of CPUs which
2119 logical grouping of CPUs that share some state, then level 1 is that group of
2120 CPUs (for example, a cluster), and level 2 is a group of clusters (for
2635 ``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*,
2669 group 0 Register*, is read to determine the id of the pending interrupt. The id
2675 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1
2676 Register* is read to determine the id of the group 1 interrupt. This id
2682 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt
2707 Acknowledge Register group 0*. If the API is invoked from S-EL1, the function
2709 group 1*. The read changes the state of the highest pending interrupt from
2753 and Non-secure interrupts as Group1 interrupts. It reads the group value
2755 (``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt.