Lines Matching refs:reset
175 The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
176 the secondary CPUs holding pen to work properly. Unfortunately, its reset value
372 Running on the Foundation FVP with reset to BL1 entrypoint
408 Running on the AEMv8 Base FVP with reset to BL1 entrypoint
432 Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
460 Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
478 Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
497 Running on the AEMv8 Base FVP with reset to BL31 entrypoint
532 - Since a FIP is not loaded when using BL31 as reset entrypoint, the
545 reset vector for each core.
553 Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
594 Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
622 Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint