Lines Matching refs:regs
31 struct ddr_cfg_regs *regs, in cal_csn_config() argument
59 regs->cs[i].config = ((cs_n_en & 0x1) << 31) | in cal_csn_config()
70 debug(" _config = 0x%x\n", regs->cs[i].config); in cal_csn_config()
90 struct ddr_cfg_regs *regs, in cal_timing_cfg() argument
228 regs->timing_cfg[0] = (((trwt_mclk & 0x3) << 30) | in cal_timing_cfg()
236 debug("timing_cfg[0] = 0x%x\n", regs->timing_cfg[0]); in cal_timing_cfg()
253 regs->timing_cfg[1] = (((pretoact_mclk & 0x0F) << 28) | in cal_timing_cfg()
261 debug("timing_cfg[1] = 0x%x\n", regs->timing_cfg[1]); in cal_timing_cfg()
270 regs->timing_cfg[2] = (((additive_latency & 0xf) << 28) | in cal_timing_cfg()
278 debug("timing_cfg[2] = 0x%x\n", regs->timing_cfg[2]); in cal_timing_cfg()
280 regs->timing_cfg[3] = (((ext_pretoact & 0x1) << 28) | in cal_timing_cfg()
288 debug("timing_cfg[3] = 0x%x\n", regs->timing_cfg[3]); in cal_timing_cfg()
290 regs->timing_cfg[4] = (((rwt_same_cs & 0xf) << 28) | in cal_timing_cfg()
299 debug("timing_cfg[4] = 0x%x\n", regs->timing_cfg[4]); in cal_timing_cfg()
306 regs->timing_cfg[5] = (((rodt_on & 0x1f) << 24) | in cal_timing_cfg()
310 debug("timing_cfg[5] = 0x%x\n", regs->timing_cfg[5]); in cal_timing_cfg()
312 regs->timing_cfg[6] = (((hs_caslat & 0x1f) << 24) | in cal_timing_cfg()
317 debug("timing_cfg[6] = 0x%x\n", regs->timing_cfg[6]); in cal_timing_cfg()
320 par_lat = (regs->sdram_rcw[1] & 0xf) + 1; in cal_timing_cfg()
324 regs->timing_cfg[7] = (((cke_rst & 0x3) << 28) | in cal_timing_cfg()
329 debug("timing_cfg[7] = 0x%x\n", regs->timing_cfg[7]); in cal_timing_cfg()
341 regs->timing_cfg[8] = (((rwt_bg & 0xf) << 28) | in cal_timing_cfg()
348 debug("timing_cfg[8] = 0x%x\n", regs->timing_cfg[8]); in cal_timing_cfg()
350 regs->timing_cfg[9] = (refrec_cid_mclk & 0x3ff) << 16 | in cal_timing_cfg()
352 debug("timing_cfg[9] = 0x%x\n", regs->timing_cfg[9]); in cal_timing_cfg()
356 struct ddr_cfg_regs *regs, in cal_ddr_sdram_rcw() argument
377 rc0f = (regs->sdram_cfg[1] & SDRAM_CFG2_AP_EN) ? rc0f : 4; in cal_ddr_sdram_rcw()
378 regs->sdram_rcw[0] = in cal_ddr_sdram_rcw()
387 regs->sdram_rcw[1] = in cal_ddr_sdram_rcw()
396 regs->sdram_rcw[2] = in cal_ddr_sdram_rcw()
399 debug("sdram_rcw[0] = 0x%x\n", regs->sdram_rcw[0]); in cal_ddr_sdram_rcw()
400 debug("sdram_rcw[1] = 0x%x\n", regs->sdram_rcw[1]); in cal_ddr_sdram_rcw()
401 debug("sdram_rcw[2] = 0x%x\n", regs->sdram_rcw[2]); in cal_ddr_sdram_rcw()
405 struct ddr_cfg_regs *regs, in cal_ddr_sdram_cfg() argument
450 regs->sdram_cfg[0] = ((mem_en & 0x1) << 31) | in cal_ddr_sdram_cfg()
468 debug("sdram_cfg[0] = 0x%x\n", regs->sdram_cfg[0]); in cal_ddr_sdram_cfg()
478 regs->sdram_cfg[1] = (0 in cal_ddr_sdram_cfg()
493 debug("sdram_cfg[1] = 0x%x\n", regs->sdram_cfg[1]); in cal_ddr_sdram_cfg()
495 regs->sdram_cfg[2] = (rd_pre & 0x1) << 16 | in cal_ddr_sdram_cfg()
501 regs->sdram_cfg[2] |= ((pdimm->package_3ds + 1) >> 1) in cal_ddr_sdram_cfg()
505 debug("sdram_cfg[2] = 0x%x\n", regs->sdram_cfg[2]); in cal_ddr_sdram_cfg()
510 struct ddr_cfg_regs *regs, in cal_ddr_sdram_interval() argument
517 regs->interval = ((refint & 0xFFFF) << 16) | in cal_ddr_sdram_interval()
519 debug("interval = 0x%x\n", regs->interval); in cal_ddr_sdram_interval()
524 struct ddr_cfg_regs *regs, in cal_ddr_sdram_mode() argument
633 regs->sdram_mode[0] = (((esdmode & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
635 debug("sdram_mode[0] = 0x%x\n", regs->sdram_mode[0]); in cal_ddr_sdram_mode()
673 regs->sdram_mode[1] = ((esdmode2 & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
675 debug("sdram_mode[1] = 0x%x\n", regs->sdram_mode[1]); in cal_ddr_sdram_mode()
684 regs->sdram_mode[9] = ((esdmode6 & 0xffff) << 16) | in cal_ddr_sdram_mode()
686 debug("sdram_mode[9] = 0x%x\n", regs->sdram_mode[9]); in cal_ddr_sdram_mode()
736 ((regs->cs[i].config & SDRAM_CS_CONFIG_EN) != 0)) { in cal_ddr_sdram_mode()
741 if (((regs->sdram_cfg[1] & SDRAM_CFG2_AP_EN) != 0) && in cal_ddr_sdram_mode()
756 regs->sdram_mode[8] = ((esdmode4 & 0xffff) << 16) | in cal_ddr_sdram_mode()
758 debug("sdram_mode[8] = 0x%x\n", regs->sdram_mode[8]); in cal_ddr_sdram_mode()
761 regs->sdram_mode[2] = (((esdmode & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
763 regs->sdram_mode[3] = ((esdmode2 & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
765 regs->sdram_mode[10] = ((esdmode4 & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
767 regs->sdram_mode[11] = ((esdmode6 & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
769 debug("sdram_mode[2] = 0x%x\n", regs->sdram_mode[2]); in cal_ddr_sdram_mode()
770 debug("sdram_mode[3] = 0x%x\n", regs->sdram_mode[3]); in cal_ddr_sdram_mode()
771 debug("sdram_mode[10] = 0x%x\n", regs->sdram_mode[10]); in cal_ddr_sdram_mode()
772 debug("sdram_mode[11] = 0x%x\n", regs->sdram_mode[11]); in cal_ddr_sdram_mode()
775 regs->sdram_mode[4] = (((esdmode & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
777 regs->sdram_mode[5] = ((esdmode2 & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
779 regs->sdram_mode[12] = ((esdmode4 & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
781 regs->sdram_mode[13] = ((esdmode6 & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
783 debug("sdram_mode[4] = 0x%x\n", regs->sdram_mode[4]); in cal_ddr_sdram_mode()
784 debug("sdram_mode[5] = 0x%x\n", regs->sdram_mode[5]); in cal_ddr_sdram_mode()
785 debug("sdram_mode[12] = 0x%x\n", regs->sdram_mode[12]); in cal_ddr_sdram_mode()
786 debug("sdram_mode[13] = 0x%x\n", regs->sdram_mode[13]); in cal_ddr_sdram_mode()
789 regs->sdram_mode[6] = (((esdmode & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
791 regs->sdram_mode[7] = ((esdmode2 & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
793 regs->sdram_mode[14] = ((esdmode4 & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
795 regs->sdram_mode[15] = ((esdmode6 & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
797 debug("sdram_mode[6] = 0x%x\n", regs->sdram_mode[6]); in cal_ddr_sdram_mode()
798 debug("sdram_mode[7] = 0x%x\n", regs->sdram_mode[7]); in cal_ddr_sdram_mode()
799 debug("sdram_mode[14] = 0x%x\n", regs->sdram_mode[14]); in cal_ddr_sdram_mode()
800 debug("sdram_mode[15] = 0x%x\n", regs->sdram_mode[15]); in cal_ddr_sdram_mode()
811 static void cal_ddr_data_init(struct ddr_cfg_regs *regs) in cal_ddr_data_init() argument
813 regs->data_init = CONFIG_MEM_INIT_VALUE; in cal_ddr_data_init()
816 static void cal_ddr_dq_mapping(struct ddr_cfg_regs *regs, in cal_ddr_dq_mapping() argument
819 const unsigned int acc_ecc_en = (regs->sdram_cfg[0] >> 2) & 0x1; in cal_ddr_dq_mapping()
821 regs->dq_map[0] = ((pdimm->dq_mapping[0] & 0x3F) << 26) | in cal_ddr_dq_mapping()
827 regs->dq_map[1] = ((pdimm->dq_mapping[5] & 0x3F) << 26) | in cal_ddr_dq_mapping()
833 regs->dq_map[2] = ((pdimm->dq_mapping[12] & 0x3F) << 26) | in cal_ddr_dq_mapping()
840 regs->dq_map[3] = ((pdimm->dq_mapping[17] & 0x3F) << 26) | in cal_ddr_dq_mapping()
845 debug("dq_map[0] = 0x%x\n", regs->dq_map[0]); in cal_ddr_dq_mapping()
846 debug("dq_map[1] = 0x%x\n", regs->dq_map[1]); in cal_ddr_dq_mapping()
847 debug("dq_map[2] = 0x%x\n", regs->dq_map[2]); in cal_ddr_dq_mapping()
848 debug("dq_map[3] = 0x%x\n", regs->dq_map[3]); in cal_ddr_dq_mapping()
850 static void cal_ddr_zq_cntl(struct ddr_cfg_regs *regs) in cal_ddr_zq_cntl() argument
858 regs->zq_cntl = ((zq_en & 0x1) << 31) | in cal_ddr_zq_cntl()
863 debug("zq_cntl = 0x%x\n", regs->zq_cntl); in cal_ddr_zq_cntl()
866 static void cal_ddr_sr_cntr(struct ddr_cfg_regs *regs, in cal_ddr_sr_cntr() argument
872 regs->ddr_sr_cntr = (sr_it & 0xF) << 16; in cal_ddr_sr_cntr()
873 debug("ddr_sr_cntr = 0x%x\n", regs->ddr_sr_cntr); in cal_ddr_sr_cntr()
876 static void cal_ddr_eor(struct ddr_cfg_regs *regs, in cal_ddr_eor() argument
880 regs->eor = 0x40000000; /* address hash enable */ in cal_ddr_eor()
881 debug("eor = 0x%x\n", regs->eor); in cal_ddr_eor()
885 static void cal_ddr_csn_bnds(struct ddr_cfg_regs *regs, in cal_ddr_csn_bnds() argument
903 regs->cs[i].bnds = ((sa & 0xffff) << 16) | in cal_ddr_csn_bnds()
905 cal_csn_config(i, regs, popts, pdimm); in cal_ddr_csn_bnds()
908 regs->cs[i].bnds = 0xffffffff; in cal_ddr_csn_bnds()
911 debug("cs[%d].bnds = 0x%x\n", i, regs->cs[i].bnds); in cal_ddr_csn_bnds()
915 static void cal_ddr_addr_dec(struct ddr_cfg_regs *regs) in cal_ddr_addr_dec() argument
920 const unsigned int cs0_config = regs->cs[0].config; in cal_ddr_addr_dec()
950 ba_intlv = (regs->sdram_cfg[0] >> 8) & 0x7f; in cal_ddr_addr_dec()
971 dbw = (regs->sdram_cfg[0] >> 19) & 0x3; in cal_ddr_addr_dec()
1101 regs->dec[0] = map_row[17] << 26 | in cal_ddr_addr_dec()
1105 regs->dec[1] = map_row[13] << 26 | in cal_ddr_addr_dec()
1109 regs->dec[2] = map_row[9] << 26 | in cal_ddr_addr_dec()
1113 regs->dec[3] = map_row[5] << 26 | in cal_ddr_addr_dec()
1117 regs->dec[4] = map_row[1] << 26 | in cal_ddr_addr_dec()
1121 regs->dec[5] = map_col[8] << 26 | in cal_ddr_addr_dec()
1125 regs->dec[6] = map_col[4] << 26 | in cal_ddr_addr_dec()
1129 regs->dec[7] = map_col[0] << 26 | in cal_ddr_addr_dec()
1133 regs->dec[8] = map_cid[1] << 26 | in cal_ddr_addr_dec()
1137 regs->dec[9] = map_bg[0] << 26 | in cal_ddr_addr_dec()
1140 debug("dec[%d] = 0x%x\n", i, regs->dec[i]); in cal_ddr_addr_dec()
1325 struct ddr_cfg_regs *regs, in compute_ddrc() argument
1335 zeromem(regs, sizeof(struct ddr_cfg_regs)); in compute_ddrc()
1374 cal_ddr_csn_bnds(regs, popts, conf, pdimm); in compute_ddrc()
1375 cal_ddr_sdram_cfg(clk, regs, popts, pdimm, ip_rev); in compute_ddrc()
1376 cal_ddr_sdram_rcw(clk, regs, popts, pdimm); in compute_ddrc()
1377 cal_timing_cfg(clk, regs, popts, pdimm, conf, cas_latency, in compute_ddrc()
1379 cal_ddr_dq_mapping(regs, pdimm); in compute_ddrc()
1382 cal_ddr_addr_dec(regs); in compute_ddrc()
1385 cal_ddr_sdram_mode(clk, regs, popts, conf, pdimm, cas_latency, in compute_ddrc()
1387 cal_ddr_eor(regs, popts); in compute_ddrc()
1388 cal_ddr_data_init(regs); in compute_ddrc()
1389 cal_ddr_sdram_interval(clk, regs, popts, pdimm); in compute_ddrc()
1390 cal_ddr_zq_cntl(regs); in compute_ddrc()
1391 cal_ddr_sr_cntr(regs, popts); in compute_ddrc()