Lines Matching refs:basic
597 if (input->basic.dimm_type != RDIMM) { in prog_acsm_playback()
623 if (input->basic.dimm_type != RDIMM) { in prog_acsm_ctr()
661 frq = input->basic.frequency >> 1; in prog_seq0bdly0()
663 if (input->basic.frequency < 400) { in prog_seq0bdly0()
664 lower_freq_opt = (input->basic.dimm_type == RDIMM) ? 7 : 3; in prog_seq0bdly0()
665 } else if (input->basic.frequency < 533) { in prog_seq0bdly0()
666 lower_freq_opt = (input->basic.dimm_type == RDIMM) ? 14 : 11; in prog_seq0bdly0()
728 load_pieimage(phy, input->basic.dimm_type); in i_load_pie()
744 input->basic.dimm_type == RDIMM && in i_load_pie()
756 input->basic.dimm_type == RDIMM ? U(0x2) : 0U); in i_load_pie()
798 if (input->basic.dimm_type == RDIMM) { in phy_gen2_init_input()
821 switch (input->basic.dimm_type) { in phy_gen2_msg_init()
848 if (input->basic.dimm_type == LRDIMM) { in phy_gen2_msg_init()
874 msg_blk->enabled_dqs = (input->basic.num_active_dbyte_dfi0 + in phy_gen2_msg_init()
875 input->basic.num_active_dbyte_dfi1) * 8; in phy_gen2_msg_init()
876 msg_blk->x16present = input->basic.dram_data_width == 0x10 ? in phy_gen2_msg_init()
902 msg_blk->dramfreq = input->basic.frequency * 2U; in phy_gen2_msg_init()
903 msg_blk->pll_bypass_en = input->basic.pll_bypass; in phy_gen2_msg_init()
904 msg_blk->dfi_freq_ratio = input->basic.dfi_freq_ratio == 0U ? 1U : in phy_gen2_msg_init()
905 input->basic.dfi_freq_ratio == 1U ? 2U : in phy_gen2_msg_init()
929 if (input->basic.dimm_type == RDIMM || in phy_gen2_msg_init()
930 input->basic.dimm_type == LRDIMM) { in phy_gen2_msg_init()
970 if (input->basic.dimm_type == LRDIMM) { in phy_gen2_msg_init()
980 if (input->basic.train2d != 0) { in phy_gen2_msg_init()
1018 for (byte = 0; byte < input->basic.num_dbyte; byte++) { in prog_tx_pre_drv_mode()
1040 if (input->basic.num_anib == 8) { in prog_atx_pre_drv_mode()
1043 } else if (input->basic.num_anib == 10 || input->basic.num_anib == 12 || in prog_atx_pre_drv_mode()
1044 input->basic.num_anib == 13) { in prog_atx_pre_drv_mode()
1048 ERROR("Invalid number of aNIBs: %d\n", input->basic.num_anib); in prog_atx_pre_drv_mode()
1052 for (anib = 0; anib < input->basic.num_anib; anib++) { in prog_atx_pre_drv_mode()
1072 if (input->basic.dimm_type != RDIMM && in prog_enable_cs_multicast()
1073 input->basic.dimm_type != LRDIMM) { in prog_enable_cs_multicast()
1107 switch (input->basic.dimm_type) { in prog_dfi_rd_data_cs_dest_map()
1180 if (input->basic.frequency / 2 < 235) { in prog_pll_ctrl2()
1182 } else if (input->basic.frequency / 2 < 313) { in prog_pll_ctrl2()
1184 } else if (input->basic.frequency / 2 < 469) { in prog_pll_ctrl2()
1186 } else if (input->basic.frequency / 2 < 625) { in prog_pll_ctrl2()
1188 } else if (input->basic.frequency / 2 < 938) { in prog_pll_ctrl2()
1190 } else if (input->basic.frequency / 2 < 1067) { in prog_pll_ctrl2()
1234 if (input->basic.frequency >= 933) { in prog_ard_ptr_init_val()
1279 } else if (input->basic.frequency <= 933) { in prog_proc_odt_time_ctl()
1281 } else if (input->basic.frequency <= 1200) { in prog_proc_odt_time_ctl()
1370 input->basic.hard_macro_ver); in prog_tx_odt_drv_stren()
1377 for (byte = 0; byte < input->basic.num_dbyte; byte++) { in prog_tx_odt_drv_stren()
1445 input->basic.hard_macro_ver); in prog_tx_impedance_ctrl1()
1447 input->basic.hard_macro_ver); in prog_tx_impedance_ctrl1()
1451 for (byte = 0; byte < input->basic.num_dbyte; byte++) { in prog_tx_impedance_ctrl1()
1543 if (input->basic.hard_macro_ver == 4 && in prog_atx_impedance()
1550 input->basic.hard_macro_ver); in prog_atx_impedance()
1552 input->basic.hard_macro_ver); in prog_atx_impedance()
1555 for (anib = 0; anib < input->basic.num_anib; anib++) { in prog_atx_impedance()
1568 if (input->basic.dfi1exists == 1) { in prog_dfi_mode()
1617 cal_uclk_ticks_per1u_s = input->basic.frequency >> 1; in prog_cal_uclk_info()
1681 for (byte = 0; byte < input->basic.num_dbyte; byte++) { in prog_dq_dqs_rcv_cntrl()
1705 if (input->basic.dram_type == DDR4 && input->adv.mem_alert_en == 1) { in prog_mem_alert_control()
1731 dfi_freq_ratio = input->basic.dfi_freq_ratio; in prog_dfi_freq_ratio()
1761 pllbypass_dat = input->basic.pll_bypass; /* only [0] is used */ in prog_dfi_xlat()
1791 for (byte = 0; byte < input->basic.num_dbyte; byte++) { in prog_dbyte_misc_mode()
1793 if (byte <= input->basic.num_active_dbyte_dfi0 - 1) { in prog_dbyte_misc_mode()
1795 if ((input->basic.dram_data_width != 4) && in prog_dbyte_misc_mode()
1818 x4tg = input->basic.dram_data_width == 4 ? 0xf : 0; in prog_master_x4config()
2193 switch (input->basic.dimm_type) { in load_fw()
2387 printf("\n \"dram_type\": \"%s\",", dram_types_str[input->basic.dram_type]); in print_jason_format()
2388 printf("\n \"dimm_type\": \"%s\",", dimm_types_str[input->basic.dimm_type]); in print_jason_format()
2389 printf("\n \"hard_macro_ver\": \"%d\",", input->basic.hard_macro_ver); in print_jason_format()
2390 printf("\n \"num_dbyte\": \"0x%04x\",", (unsigned int)input->basic.num_dbyte); in print_jason_format()
2391 …printf("\n \"num_active_dbyte_dfi0\": \"0x%04x\",", (unsigned int)input->basic.num_active_dbyte… in print_jason_format()
2392 printf("\n \"num_anib\": \"0x%04x\",", (unsigned int)input->basic.num_anib); in print_jason_format()
2393 printf("\n \"num_rank_dfi0\": \"0x%04x\",", (unsigned int)input->basic.num_rank_dfi0); in print_jason_format()
2394 printf("\n \"num_pstates\": \"0x%04x\",", (unsigned int)input->basic.num_pstates); in print_jason_format()
2395 printf("\n \"frequency\": \"%d\",", input->basic.frequency); in print_jason_format()
2396 printf("\n \"pll_bypass\": \"0x%04x\",", (unsigned int)input->basic.dfi_freq_ratio); in print_jason_format()
2397 printf("\n \"dfi_freq_ratio\": \"0x%04x\",", (unsigned int)input->basic.dfi_freq_ratio); in print_jason_format()
2398 printf("\n \"dfi1_exists\": \"0x%04x\",", (unsigned int)input->basic.dfi1exists); in print_jason_format()
2399 printf("\n \"dram_data_width\": \"0x%04x\",", (unsigned int)input->basic.dram_data_width); in print_jason_format()
2487 input.basic.dram_type = DDR4; in compute_ddr_phy()
2489 input.basic.dimm_type = (dimm_param->rdimm != 0) ? RDIMM : UDIMM; in compute_ddr_phy()
2490 input.basic.num_dbyte = dimm_param->primary_sdram_width / 8 + in compute_ddr_phy()
2492 input.basic.num_active_dbyte_dfi0 = input.basic.num_dbyte; in compute_ddr_phy()
2493 input.basic.num_rank_dfi0 = dimm_param->n_ranks; in compute_ddr_phy()
2494 input.basic.dram_data_width = dimm_param->device_width; in compute_ddr_phy()
2495 input.basic.hard_macro_ver = 0xa; in compute_ddr_phy()
2496 input.basic.num_pstates = 1; in compute_ddr_phy()
2497 input.basic.dfi_freq_ratio = 1; in compute_ddr_phy()
2498 input.basic.num_anib = 0xc; in compute_ddr_phy()
2499 input.basic.train2d = popts->skip2d ? 0 : 1; in compute_ddr_phy()
2500 input.basic.frequency = (int) (clk / 2000000ul); in compute_ddr_phy()
2501 debug("frequency = %dMHz\n", input.basic.frequency); in compute_ddr_phy()
2580 input.basic.train2d); in compute_ddr_phy()
2609 get_cdd_val(priv->phy, rank, input.basic.frequency, in compute_ddr_phy()
2616 if ((ret == 0) && (input.basic.train2d != 0)) { in compute_ddr_phy()
2643 input.basic.train2d); in compute_ddr_phy()
2657 input.basic.dimm_type == RDIMM ? "RDIMM" : in compute_ddr_phy()
2658 input.basic.dimm_type == LRDIMM ? "LRDIMM" : in compute_ddr_phy()