Lines Matching refs:input
588 const struct input *input, const void *msg) in prog_acsm_playback() argument
597 if (input->basic.dimm_type != RDIMM) { in prog_acsm_playback()
604 f0rc5x = (input->adv.phy_gen2_umctl_f0rc5x & U(0xff)) | U(0x500); in prog_acsm_playback()
621 const struct input *input) in prog_acsm_ctr() argument
623 if (input->basic.dimm_type != RDIMM) { in prog_acsm_ctr()
635 const struct input *input) in prog_cal_rate_run() argument
642 cal_interval = input->adv.cal_interval; in prog_cal_rate_run()
643 cal_once = input->adv.cal_once; in prog_cal_rate_run()
652 const struct input *input) in prog_seq0bdly0() argument
661 frq = input->basic.frequency >> 1; in prog_seq0bdly0()
663 if (input->basic.frequency < 400) { in prog_seq0bdly0()
664 lower_freq_opt = (input->basic.dimm_type == RDIMM) ? 7 : 3; in prog_seq0bdly0()
665 } else if (input->basic.frequency < 533) { in prog_seq0bdly0()
666 lower_freq_opt = (input->basic.dimm_type == RDIMM) ? 14 : 11; in prog_seq0bdly0()
712 const struct input *input, in i_load_pie() argument
728 load_pieimage(phy, input->basic.dimm_type); in i_load_pie()
730 prog_seq0bdly0(phy, input); in i_load_pie()
744 input->basic.dimm_type == RDIMM && in i_load_pie()
745 input->adv.phy_gen2_umctl_opt == 1U ? in i_load_pie()
749 prog_acsm_playback(phy, input, msg); /* rdimm */ in i_load_pie()
750 prog_acsm_ctr(phy, input); /* rdimm */ in i_load_pie()
753 prog_cal_rate_run(phy, input); in i_load_pie()
756 input->basic.dimm_type == RDIMM ? U(0x2) : 0U); in i_load_pie()
762 static void phy_gen2_init_input(struct input *input) in phy_gen2_init_input() argument
766 input->adv.dram_byte_swap = 0; in phy_gen2_init_input()
767 input->adv.ext_cal_res_val = 0; in phy_gen2_init_input()
768 input->adv.tx_slew_rise_dq = 0xf; in phy_gen2_init_input()
769 input->adv.tx_slew_fall_dq = 0xf; in phy_gen2_init_input()
770 input->adv.tx_slew_rise_ac = 0xf; in phy_gen2_init_input()
771 input->adv.tx_slew_fall_ac = 0xf; in phy_gen2_init_input()
772 input->adv.mem_alert_en = 0; in phy_gen2_init_input()
773 input->adv.mem_alert_puimp = 5; in phy_gen2_init_input()
774 input->adv.mem_alert_vref_level = 0x29; in phy_gen2_init_input()
775 input->adv.mem_alert_sync_bypass = 0; in phy_gen2_init_input()
776 input->adv.cal_interval = 0x9; in phy_gen2_init_input()
777 input->adv.cal_once = 0; in phy_gen2_init_input()
778 input->adv.dis_dyn_adr_tri = 0; in phy_gen2_init_input()
779 input->adv.is2ttiming = 0; in phy_gen2_init_input()
780 input->adv.d4rx_preamble_length = 0; in phy_gen2_init_input()
781 input->adv.d4tx_preamble_length = 0; in phy_gen2_init_input()
784 debug("mr[%d] = 0x%x\n", i, input->mr[i]); in phy_gen2_init_input()
787 debug("input->cs_d0 = 0x%x\n", input->cs_d0); in phy_gen2_init_input()
788 debug("input->cs_d1 = 0x%x\n", input->cs_d1); in phy_gen2_init_input()
789 debug("input->mirror = 0x%x\n", input->mirror); in phy_gen2_init_input()
790 debug("PHY ODT impedance = %d ohm\n", input->adv.odtimpedance); in phy_gen2_init_input()
791 debug("PHY DQ driver impedance = %d ohm\n", input->adv.tx_impedance); in phy_gen2_init_input()
792 debug("PHY Addr driver impedance = %d ohm\n", input->adv.atx_impedance); in phy_gen2_init_input()
795 debug("odt[%d] = 0x%x\n", i, input->odt[i]); in phy_gen2_init_input()
798 if (input->basic.dimm_type == RDIMM) { in phy_gen2_init_input()
800 debug("input->rcw[%d] = 0x%x\n", i, input->rcw[i]); in phy_gen2_init_input()
802 debug("input->rcw3x = 0x%x\n", input->rcw3x); in phy_gen2_init_input()
814 const struct input *input) in phy_gen2_msg_init() argument
821 switch (input->basic.dimm_type) { in phy_gen2_msg_init()
848 if (input->basic.dimm_type == LRDIMM) { in phy_gen2_msg_init()
861 msg_blk->phy_vref = input->vref ? input->vref : U(0x61); in phy_gen2_msg_init()
862 msg_blk->cs_present = input->cs_d0 | input->cs_d1; in phy_gen2_msg_init()
863 msg_blk->cs_present_d0 = input->cs_d0; in phy_gen2_msg_init()
864 msg_blk->cs_present_d1 = input->cs_d1; in phy_gen2_msg_init()
865 if (input->mirror != 0) { in phy_gen2_msg_init()
870 msg_blk->acsm_odt_ctrl0 = input->odt[0]; in phy_gen2_msg_init()
871 msg_blk->acsm_odt_ctrl1 = input->odt[1]; in phy_gen2_msg_init()
872 msg_blk->acsm_odt_ctrl2 = input->odt[2]; in phy_gen2_msg_init()
873 msg_blk->acsm_odt_ctrl3 = input->odt[3]; in phy_gen2_msg_init()
874 msg_blk->enabled_dqs = (input->basic.num_active_dbyte_dfi0 + in phy_gen2_msg_init()
875 input->basic.num_active_dbyte_dfi1) * 8; in phy_gen2_msg_init()
876 msg_blk->x16present = input->basic.dram_data_width == 0x10 ? in phy_gen2_msg_init()
888 msg_blk->mr0 = input->mr[0]; in phy_gen2_msg_init()
889 msg_blk->mr1 = input->mr[1]; in phy_gen2_msg_init()
890 msg_blk->mr2 = input->mr[2]; in phy_gen2_msg_init()
891 msg_blk->mr3 = input->mr[3]; in phy_gen2_msg_init()
892 msg_blk->mr4 = input->mr[4]; in phy_gen2_msg_init()
893 msg_blk->mr5 = input->mr[5]; in phy_gen2_msg_init()
894 msg_blk->mr6 = input->mr[6]; in phy_gen2_msg_init()
902 msg_blk->dramfreq = input->basic.frequency * 2U; in phy_gen2_msg_init()
903 msg_blk->pll_bypass_en = input->basic.pll_bypass; in phy_gen2_msg_init()
904 msg_blk->dfi_freq_ratio = input->basic.dfi_freq_ratio == 0U ? 1U : in phy_gen2_msg_init()
905 input->basic.dfi_freq_ratio == 1U ? 2U : in phy_gen2_msg_init()
907 msg_blk->bpznres_val = input->adv.ext_cal_res_val; in phy_gen2_msg_init()
929 if (input->basic.dimm_type == RDIMM || in phy_gen2_msg_init()
930 input->basic.dimm_type == LRDIMM) { in phy_gen2_msg_init()
933 msg_blk_r->f0rc00_d0 = input->rcw[0]; in phy_gen2_msg_init()
934 msg_blk_r->f0rc01_d0 = input->rcw[1]; in phy_gen2_msg_init()
935 msg_blk_r->f0rc02_d0 = input->rcw[2]; in phy_gen2_msg_init()
936 msg_blk_r->f0rc03_d0 = input->rcw[3]; in phy_gen2_msg_init()
937 msg_blk_r->f0rc04_d0 = input->rcw[4]; in phy_gen2_msg_init()
938 msg_blk_r->f0rc05_d0 = input->rcw[5]; in phy_gen2_msg_init()
939 msg_blk_r->f0rc06_d0 = input->rcw[6]; in phy_gen2_msg_init()
940 msg_blk_r->f0rc07_d0 = input->rcw[7]; in phy_gen2_msg_init()
941 msg_blk_r->f0rc08_d0 = input->rcw[8]; in phy_gen2_msg_init()
942 msg_blk_r->f0rc09_d0 = input->rcw[9]; in phy_gen2_msg_init()
943 msg_blk_r->f0rc0a_d0 = input->rcw[10]; in phy_gen2_msg_init()
944 msg_blk_r->f0rc0b_d0 = input->rcw[11]; in phy_gen2_msg_init()
945 msg_blk_r->f0rc0c_d0 = input->rcw[12]; in phy_gen2_msg_init()
946 msg_blk_r->f0rc0d_d0 = input->rcw[13]; in phy_gen2_msg_init()
947 msg_blk_r->f0rc0e_d0 = input->rcw[14]; in phy_gen2_msg_init()
948 msg_blk_r->f0rc0f_d0 = input->rcw[15]; in phy_gen2_msg_init()
949 msg_blk_r->f0rc3x_d0 = input->rcw3x; in phy_gen2_msg_init()
952 msg_blk_r->f0rc00_d1 = input->rcw[0]; in phy_gen2_msg_init()
953 msg_blk_r->f0rc01_d1 = input->rcw[1]; in phy_gen2_msg_init()
954 msg_blk_r->f0rc02_d1 = input->rcw[2]; in phy_gen2_msg_init()
955 msg_blk_r->f0rc03_d1 = input->rcw[3]; in phy_gen2_msg_init()
956 msg_blk_r->f0rc04_d1 = input->rcw[4]; in phy_gen2_msg_init()
957 msg_blk_r->f0rc05_d1 = input->rcw[5]; in phy_gen2_msg_init()
958 msg_blk_r->f0rc06_d1 = input->rcw[6]; in phy_gen2_msg_init()
959 msg_blk_r->f0rc07_d1 = input->rcw[7]; in phy_gen2_msg_init()
960 msg_blk_r->f0rc08_d1 = input->rcw[8]; in phy_gen2_msg_init()
961 msg_blk_r->f0rc09_d1 = input->rcw[9]; in phy_gen2_msg_init()
962 msg_blk_r->f0rc0a_d1 = input->rcw[10]; in phy_gen2_msg_init()
963 msg_blk_r->f0rc0b_d1 = input->rcw[11]; in phy_gen2_msg_init()
964 msg_blk_r->f0rc0c_d1 = input->rcw[12]; in phy_gen2_msg_init()
965 msg_blk_r->f0rc0d_d1 = input->rcw[13]; in phy_gen2_msg_init()
966 msg_blk_r->f0rc0e_d1 = input->rcw[14]; in phy_gen2_msg_init()
967 msg_blk_r->f0rc0f_d1 = input->rcw[15]; in phy_gen2_msg_init()
968 msg_blk_r->f0rc3x_d1 = input->rcw3x; in phy_gen2_msg_init()
970 if (input->basic.dimm_type == LRDIMM) { in phy_gen2_msg_init()
980 if (input->basic.train2d != 0) { in phy_gen2_msg_init()
997 : input->adv.is2ttiming; in phy_gen2_msg_init()
1003 const struct input *input) in prog_tx_pre_drv_mode() argument
1012 tx_pre_p = input->adv.tx_slew_rise_dq; in prog_tx_pre_drv_mode()
1013 tx_pre_n = input->adv.tx_slew_fall_dq; in prog_tx_pre_drv_mode()
1018 for (byte = 0; byte < input->basic.num_dbyte; byte++) { in prog_tx_pre_drv_mode()
1030 const struct input *input) in prog_atx_pre_drv_mode() argument
1037 atx_pre_n = input->adv.tx_slew_fall_ac; in prog_atx_pre_drv_mode()
1038 atx_pre_p = input->adv.tx_slew_rise_ac; in prog_atx_pre_drv_mode()
1040 if (input->basic.num_anib == 8) { in prog_atx_pre_drv_mode()
1043 } else if (input->basic.num_anib == 10 || input->basic.num_anib == 12 || in prog_atx_pre_drv_mode()
1044 input->basic.num_anib == 13) { in prog_atx_pre_drv_mode()
1048 ERROR("Invalid number of aNIBs: %d\n", input->basic.num_anib); in prog_atx_pre_drv_mode()
1052 for (anib = 0; anib < input->basic.num_anib; anib++) { in prog_atx_pre_drv_mode()
1068 const struct input *input) in prog_enable_cs_multicast() argument
1072 if (input->basic.dimm_type != RDIMM && in prog_enable_cs_multicast()
1073 input->basic.dimm_type != LRDIMM) { in prog_enable_cs_multicast()
1077 phy_io_write16(phy, addr, input->adv.cast_cs_to_cid); in prog_enable_cs_multicast()
1082 const struct input *input, in prog_dfi_rd_data_cs_dest_map() argument
1107 switch (input->basic.dimm_type) { in prog_dfi_rd_data_cs_dest_map()
1151 const struct input *input) in prog_pll_ctrl() argument
1175 const struct input *input) in prog_pll_ctrl2() argument
1180 if (input->basic.frequency / 2 < 235) { in prog_pll_ctrl2()
1182 } else if (input->basic.frequency / 2 < 313) { in prog_pll_ctrl2()
1184 } else if (input->basic.frequency / 2 < 469) { in prog_pll_ctrl2()
1186 } else if (input->basic.frequency / 2 < 625) { in prog_pll_ctrl2()
1188 } else if (input->basic.frequency / 2 < 938) { in prog_pll_ctrl2()
1190 } else if (input->basic.frequency / 2 < 1067) { in prog_pll_ctrl2()
1201 static void prog_dll_lck_param(uint16_t *phy, const struct input *input) in prog_dll_lck_param() argument
1209 static void prog_dll_gain_ctl(uint16_t *phy, const struct input *input) in prog_dll_gain_ctl() argument
1218 const struct input *input) in prog_pll_pwr_dn() argument
1229 const struct input *input) in prog_ard_ptr_init_val() argument
1234 if (input->basic.frequency >= 933) { in prog_ard_ptr_init_val()
1244 const struct input *input) in prog_dqs_preamble_control() argument
1254 int two_tck_tx_dqs_pre = input->adv.d4tx_preamble_length; in prog_dqs_preamble_control()
1255 int two_tck_rx_dqs_pre = input->adv.d4rx_preamble_length; in prog_dqs_preamble_control()
1272 const struct input *input) in prog_proc_odt_time_ctl() argument
1277 if (input->adv.wdqsext != 0) { in prog_proc_odt_time_ctl()
1279 } else if (input->basic.frequency <= 933) { in prog_proc_odt_time_ctl()
1281 } else if (input->basic.frequency <= 1200) { in prog_proc_odt_time_ctl()
1282 if (input->adv.d4rx_preamble_length == 1) { in prog_proc_odt_time_ctl()
1288 if (input->adv.d4rx_preamble_length == 1) { in prog_proc_odt_time_ctl()
1362 const struct input *input) in prog_tx_odt_drv_stren() argument
1369 odtstren_p = map_odtstren_p(input->adv.odtimpedance, in prog_tx_odt_drv_stren()
1370 input->basic.hard_macro_ver); in prog_tx_odt_drv_stren()
1377 for (byte = 0; byte < input->basic.num_dbyte; byte++) { in prog_tx_odt_drv_stren()
1437 const struct input *input) in prog_tx_impedance_ctrl1() argument
1444 drv_stren_fsdq_p = map_drvstren_fsdq_p(input->adv.tx_impedance, in prog_tx_impedance_ctrl1()
1445 input->basic.hard_macro_ver); in prog_tx_impedance_ctrl1()
1446 drv_stren_fsdq_n = map_drvstren_fsdq_n(input->adv.tx_impedance, in prog_tx_impedance_ctrl1()
1447 input->basic.hard_macro_ver); in prog_tx_impedance_ctrl1()
1451 for (byte = 0; byte < input->basic.num_dbyte; byte++) { in prog_tx_impedance_ctrl1()
1535 const struct input *input) in prog_atx_impedance() argument
1543 if (input->basic.hard_macro_ver == 4 && in prog_atx_impedance()
1544 input->adv.atx_impedance == 20) { in prog_atx_impedance()
1549 adrv_stren_p = map_adrv_stren_p(input->adv.atx_impedance, in prog_atx_impedance()
1550 input->basic.hard_macro_ver); in prog_atx_impedance()
1551 adrv_stren_n = map_adrv_stren_n(input->adv.atx_impedance, in prog_atx_impedance()
1552 input->basic.hard_macro_ver); in prog_atx_impedance()
1555 for (anib = 0; anib < input->basic.num_anib; anib++) { in prog_atx_impedance()
1563 const struct input *input) in prog_dfi_mode() argument
1568 if (input->basic.dfi1exists == 1) { in prog_dfi_mode()
1577 static void prog_acx4_anib_dis(uint16_t *phy, const struct input *input) in prog_acx4_anib_dis() argument
1587 const struct input *input) in prog_dfi_camode() argument
1596 const struct input *input) in prog_cal_drv_str0() argument
1603 cal_drv_str_pu50 = input->adv.ext_cal_res_val; in prog_cal_drv_str0()
1612 const struct input *input) in prog_cal_uclk_info() argument
1617 cal_uclk_ticks_per1u_s = input->basic.frequency >> 1; in prog_cal_uclk_info()
1627 const struct input *input) in prog_cal_rate() argument
1634 cal_interval = input->adv.cal_interval; in prog_cal_rate()
1635 cal_once = input->adv.cal_once; in prog_cal_rate()
1643 const struct input *input, in prog_vref_in_global() argument
1665 const struct input *input) in prog_dq_dqs_rcv_cntrl() argument
1681 for (byte = 0; byte < input->basic.num_dbyte; byte++) { in prog_dq_dqs_rcv_cntrl()
1693 const struct input *input) in prog_mem_alert_control() argument
1705 if (input->basic.dram_type == DDR4 && input->adv.mem_alert_en == 1) { in prog_mem_alert_control()
1708 malertpu_stren = input->adv.mem_alert_puimp; in prog_mem_alert_control()
1709 malertvref_level = input->adv.mem_alert_vref_level; in prog_mem_alert_control()
1710 malertsync_bypass = input->adv.mem_alert_sync_bypass; in prog_mem_alert_control()
1726 const struct input *input) in prog_dfi_freq_ratio() argument
1731 dfi_freq_ratio = input->basic.dfi_freq_ratio; in prog_dfi_freq_ratio()
1736 const struct input *input) in prog_tristate_mode_ca() argument
1744 dis_dyn_adr_tri = input->adv.dis_dyn_adr_tri; in prog_tristate_mode_ca()
1745 ddr2tmode = input->adv.is2ttiming; in prog_tristate_mode_ca()
1753 const struct input *input) in prog_dfi_xlat() argument
1761 pllbypass_dat = input->basic.pll_bypass; /* only [0] is used */ in prog_dfi_xlat()
1776 const struct input *input, in prog_dbyte_misc_mode() argument
1791 for (byte = 0; byte < input->basic.num_dbyte; byte++) { in prog_dbyte_misc_mode()
1793 if (byte <= input->basic.num_active_dbyte_dfi0 - 1) { in prog_dbyte_misc_mode()
1795 if ((input->basic.dram_data_width != 4) && in prog_dbyte_misc_mode()
1812 const struct input *input) in prog_master_x4config() argument
1818 x4tg = input->basic.dram_data_width == 4 ? 0xf : 0; in prog_master_x4config()
1824 const struct input *input, in prog_dmipin_present() argument
1835 const struct input *input) in prog_dfi_phyupd() argument
1848 const struct input *input) in prog_cal_misc2() argument
1870 const struct input *input, in c_init_phy_config() argument
1884 prog_dfi_phyupd(phy, input); in c_init_phy_config()
1885 prog_cal_misc2(phy, input); in c_init_phy_config()
1886 prog_tx_pre_drv_mode(phy, input); in c_init_phy_config()
1887 prog_atx_pre_drv_mode(phy, input); in c_init_phy_config()
1888 prog_enable_cs_multicast(phy, input); /* rdimm and lrdimm */ in c_init_phy_config()
1889 prog_dfi_rd_data_cs_dest_map(phy, ip_rev, input, msg); in c_init_phy_config()
1890 prog_pll_ctrl2(phy, input); in c_init_phy_config()
1895 prog_pll_pwr_dn(phy, input); in c_init_phy_config()
1901 prog_ard_ptr_init_val(phy, input); in c_init_phy_config()
1902 prog_dqs_preamble_control(phy, input); in c_init_phy_config()
1903 prog_dll_lck_param(phy, input); in c_init_phy_config()
1904 prog_dll_gain_ctl(phy, input); in c_init_phy_config()
1905 prog_proc_odt_time_ctl(phy, input); in c_init_phy_config()
1906 prog_tx_odt_drv_stren(phy, input); in c_init_phy_config()
1907 prog_tx_impedance_ctrl1(phy, input); in c_init_phy_config()
1908 prog_atx_impedance(phy, input); in c_init_phy_config()
1909 prog_dfi_mode(phy, input); in c_init_phy_config()
1910 prog_dfi_camode(phy, input); in c_init_phy_config()
1911 prog_cal_drv_str0(phy, input); in c_init_phy_config()
1912 prog_cal_uclk_info(phy, input); in c_init_phy_config()
1913 prog_cal_rate(phy, input); in c_init_phy_config()
1914 prog_vref_in_global(phy, input, msg); in c_init_phy_config()
1915 prog_dq_dqs_rcv_cntrl(phy, input); in c_init_phy_config()
1916 prog_mem_alert_control(phy, input); in c_init_phy_config()
1917 prog_dfi_freq_ratio(phy, input); in c_init_phy_config()
1918 prog_tristate_mode_ca(phy, input); in c_init_phy_config()
1919 prog_dfi_xlat(phy, input); in c_init_phy_config()
1920 prog_dbyte_misc_mode(phy, input, msg); in c_init_phy_config()
1921 prog_master_x4config(phy, input); in c_init_phy_config()
1922 prog_dmipin_present(phy, input, msg); in c_init_phy_config()
1923 prog_acx4_anib_dis(phy, input); in c_init_phy_config()
2121 static int g_exec_fw(uint16_t **phy_ptr, int train2d, struct input *input) in g_exec_fw() argument
2133 prog_pll_ctrl2(phy, input); in g_exec_fw()
2134 prog_pll_ctrl(phy, input); in g_exec_fw()
2178 struct input *input, in load_fw() argument
2193 switch (input->basic.dimm_type) { in load_fw()
2381 static void print_jason_format(struct input *input, in print_jason_format() argument
2387 printf("\n \"dram_type\": \"%s\",", dram_types_str[input->basic.dram_type]); in print_jason_format()
2388 printf("\n \"dimm_type\": \"%s\",", dimm_types_str[input->basic.dimm_type]); in print_jason_format()
2389 printf("\n \"hard_macro_ver\": \"%d\",", input->basic.hard_macro_ver); in print_jason_format()
2390 printf("\n \"num_dbyte\": \"0x%04x\",", (unsigned int)input->basic.num_dbyte); in print_jason_format()
2391 …printf("\n \"num_active_dbyte_dfi0\": \"0x%04x\",", (unsigned int)input->basic.num_active_dbyte… in print_jason_format()
2392 printf("\n \"num_anib\": \"0x%04x\",", (unsigned int)input->basic.num_anib); in print_jason_format()
2393 printf("\n \"num_rank_dfi0\": \"0x%04x\",", (unsigned int)input->basic.num_rank_dfi0); in print_jason_format()
2394 printf("\n \"num_pstates\": \"0x%04x\",", (unsigned int)input->basic.num_pstates); in print_jason_format()
2395 printf("\n \"frequency\": \"%d\",", input->basic.frequency); in print_jason_format()
2396 printf("\n \"pll_bypass\": \"0x%04x\",", (unsigned int)input->basic.dfi_freq_ratio); in print_jason_format()
2397 printf("\n \"dfi_freq_ratio\": \"0x%04x\",", (unsigned int)input->basic.dfi_freq_ratio); in print_jason_format()
2398 printf("\n \"dfi1_exists\": \"0x%04x\",", (unsigned int)input->basic.dfi1exists); in print_jason_format()
2399 printf("\n \"dram_data_width\": \"0x%04x\",", (unsigned int)input->basic.dram_data_width); in print_jason_format()
2400 printf("\n \"dram_byte_swap\": \"0x%04x\",", (unsigned int)input->adv.dram_byte_swap); in print_jason_format()
2401 printf("\n \"ext_cal_res_val\": \"0x%04x\",", (unsigned int)input->adv.ext_cal_res_val); in print_jason_format()
2402 printf("\n \"tx_slew_rise_dq\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_rise_dq); in print_jason_format()
2403 printf("\n \"tx_slew_fall_dq\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_fall_dq); in print_jason_format()
2404 printf("\n \"tx_slew_rise_ac\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_rise_ac); in print_jason_format()
2405 printf("\n \"tx_slew_fall_ac\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_fall_ac); in print_jason_format()
2406 printf("\n \"odt_impedance\": \"%d\",", input->adv.odtimpedance); in print_jason_format()
2407 printf("\n \"tx_impedance\": \"%d\",", input->adv.tx_impedance); in print_jason_format()
2408 printf("\n \"atx_impedance\": \"%d\",", input->adv.atx_impedance); in print_jason_format()
2409 printf("\n \"mem_alert_en\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_en); in print_jason_format()
2410 printf("\n \"mem_alert_pu_imp\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_puimp); in print_jason_format()
2411 …printf("\n \"mem_alert_vref_level\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_vref_leve… in print_jason_format()
2412 …printf("\n \"mem_alert_sync_bypass\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_sync_byp… in print_jason_format()
2413 printf("\n \"cal_interval\": \"0x%04x\",", (unsigned int)input->adv.cal_interval); in print_jason_format()
2414 printf("\n \"cal_once\": \"0x%04x\",", (unsigned int)input->adv.cal_once); in print_jason_format()
2415 printf("\n \"dis_dyn_adr_tri\": \"0x%04x\",", (unsigned int)input->adv.dis_dyn_adr_tri); in print_jason_format()
2416 printf("\n \"is2t_timing\": \"0x%04x\",", (unsigned int)input->adv.is2ttiming); in print_jason_format()
2417 …printf("\n \"d4rx_preabmle_length\": \"0x%04x\",", (unsigned int)input->adv.d4rx_preamble_lengt… in print_jason_format()
2418 …printf("\n \"d4tx_preamble_length\": \"0x%04x\",", (unsigned int)input->adv.d4tx_preamble_lengt… in print_jason_format()
2468 static struct input input; in compute_ddr_phy() local
2483 zeromem(&input, sizeof(input)); in compute_ddr_phy()
2487 input.basic.dram_type = DDR4; in compute_ddr_phy()
2489 input.basic.dimm_type = (dimm_param->rdimm != 0) ? RDIMM : UDIMM; in compute_ddr_phy()
2490 input.basic.num_dbyte = dimm_param->primary_sdram_width / 8 + in compute_ddr_phy()
2492 input.basic.num_active_dbyte_dfi0 = input.basic.num_dbyte; in compute_ddr_phy()
2493 input.basic.num_rank_dfi0 = dimm_param->n_ranks; in compute_ddr_phy()
2494 input.basic.dram_data_width = dimm_param->device_width; in compute_ddr_phy()
2495 input.basic.hard_macro_ver = 0xa; in compute_ddr_phy()
2496 input.basic.num_pstates = 1; in compute_ddr_phy()
2497 input.basic.dfi_freq_ratio = 1; in compute_ddr_phy()
2498 input.basic.num_anib = 0xc; in compute_ddr_phy()
2499 input.basic.train2d = popts->skip2d ? 0 : 1; in compute_ddr_phy()
2500 input.basic.frequency = (int) (clk / 2000000ul); in compute_ddr_phy()
2501 debug("frequency = %dMHz\n", input.basic.frequency); in compute_ddr_phy()
2502 input.cs_d0 = conf->cs_on_dimm[0]; in compute_ddr_phy()
2504 input.cs_d1 = conf->cs_on_dimm[1]; in compute_ddr_phy()
2506 input.mirror = dimm_param->mirrored_dimm; in compute_ddr_phy()
2507 input.mr[0] = regs->sdram_mode[0] & U(0xffff); in compute_ddr_phy()
2508 input.mr[1] = regs->sdram_mode[0] >> 16U; in compute_ddr_phy()
2509 input.mr[2] = regs->sdram_mode[1] >> 16U; in compute_ddr_phy()
2510 input.mr[3] = regs->sdram_mode[1] & U(0xffff); in compute_ddr_phy()
2511 input.mr[4] = regs->sdram_mode[8] >> 16U; in compute_ddr_phy()
2512 input.mr[5] = regs->sdram_mode[8] & U(0xffff); in compute_ddr_phy()
2513 input.mr[6] = regs->sdram_mode[9] >> 16U; in compute_ddr_phy()
2514 input.vref = popts->vref_phy; in compute_ddr_phy()
2515 debug("Vref_phy = %d percent\n", (input.vref * 100U) >> 7U); in compute_ddr_phy()
2522 parse_odt(odt_rd, true, i, input.cs_d0, input.cs_d1, in compute_ddr_phy()
2523 input.odt); in compute_ddr_phy()
2524 parse_odt(odt_wr, false, i, input.cs_d0, input.cs_d1, in compute_ddr_phy()
2525 input.odt); in compute_ddr_phy()
2532 input.rcw[0] = (regs->sdram_rcw[0] >> 28U) & U(0xf); in compute_ddr_phy()
2533 input.rcw[1] = (regs->sdram_rcw[0] >> 24U) & U(0xf); in compute_ddr_phy()
2534 input.rcw[2] = (regs->sdram_rcw[0] >> 20U) & U(0xf); in compute_ddr_phy()
2535 input.rcw[3] = (regs->sdram_rcw[0] >> 16U) & U(0xf); in compute_ddr_phy()
2536 input.rcw[4] = (regs->sdram_rcw[0] >> 12U) & U(0xf); in compute_ddr_phy()
2537 input.rcw[5] = (regs->sdram_rcw[0] >> 8U) & U(0xf); in compute_ddr_phy()
2538 input.rcw[6] = (regs->sdram_rcw[0] >> 4U) & U(0xf); in compute_ddr_phy()
2539 input.rcw[7] = (regs->sdram_rcw[0] >> 0U) & U(0xf); in compute_ddr_phy()
2540 input.rcw[8] = (regs->sdram_rcw[1] >> 28U) & U(0xf); in compute_ddr_phy()
2541 input.rcw[9] = (regs->sdram_rcw[1] >> 24U) & U(0xf); in compute_ddr_phy()
2542 input.rcw[10] = (regs->sdram_rcw[1] >> 20U) & U(0xf); in compute_ddr_phy()
2543 input.rcw[11] = (regs->sdram_rcw[1] >> 16U) & U(0xf); in compute_ddr_phy()
2544 input.rcw[12] = (regs->sdram_rcw[1] >> 12U) & U(0xf); in compute_ddr_phy()
2545 input.rcw[13] = (regs->sdram_rcw[1] >> 8U) & U(0xf); in compute_ddr_phy()
2546 input.rcw[14] = (regs->sdram_rcw[1] >> 4U) & U(0xf); in compute_ddr_phy()
2547 input.rcw[15] = (regs->sdram_rcw[1] >> 0U) & U(0xf); in compute_ddr_phy()
2548 input.rcw3x = (regs->sdram_rcw[2] >> 8U) & U(0xff); in compute_ddr_phy()
2551 input.adv.odtimpedance = popts->odt ? popts->odt : 60; in compute_ddr_phy()
2552 input.adv.tx_impedance = popts->phy_tx_impedance ? in compute_ddr_phy()
2554 input.adv.atx_impedance = popts->phy_atx_impedance ? in compute_ddr_phy()
2558 phy_gen2_init_input(&input); in compute_ddr_phy()
2561 ret = phy_gen2_msg_init(&msg_1d, &msg_2d, &input); in compute_ddr_phy()
2567 ret = c_init_phy_config(priv->phy, priv->ip_rev, &input, &msg_1d); in compute_ddr_phy()
2580 input.basic.train2d); in compute_ddr_phy()
2589 ret = load_fw(priv->phy, &input, 0, &msg_1d, in compute_ddr_phy()
2598 ret = g_exec_fw(priv->phy, 0, &input); in compute_ddr_phy()
2609 get_cdd_val(priv->phy, rank, input.basic.frequency, in compute_ddr_phy()
2616 if ((ret == 0) && (input.basic.train2d != 0)) { in compute_ddr_phy()
2619 ret = load_fw(priv->phy, &input, 1, &msg_2d, in compute_ddr_phy()
2628 ret = g_exec_fw(priv->phy, 1, &input); in compute_ddr_phy()
2643 input.basic.train2d); in compute_ddr_phy()
2654 i_load_pie(priv->phy, &input, &msg_1d); in compute_ddr_phy()
2657 input.basic.dimm_type == RDIMM ? "RDIMM" : in compute_ddr_phy()
2658 input.basic.dimm_type == LRDIMM ? "LRDIMM" : in compute_ddr_phy()
2665 print_jason_format(&input, &msg_1d, &msg_2d); in compute_ddr_phy()