Lines Matching refs:regs
2466 struct ddr_cfg_regs *regs = &priv->ddr_reg; in compute_ddr_phy() local
2507 input.mr[0] = regs->sdram_mode[0] & U(0xffff); in compute_ddr_phy()
2508 input.mr[1] = regs->sdram_mode[0] >> 16U; in compute_ddr_phy()
2509 input.mr[2] = regs->sdram_mode[1] >> 16U; in compute_ddr_phy()
2510 input.mr[3] = regs->sdram_mode[1] & U(0xffff); in compute_ddr_phy()
2511 input.mr[4] = regs->sdram_mode[8] >> 16U; in compute_ddr_phy()
2512 input.mr[5] = regs->sdram_mode[8] & U(0xffff); in compute_ddr_phy()
2513 input.mr[6] = regs->sdram_mode[9] >> 16U; in compute_ddr_phy()
2517 if ((regs->cs[i].config & SDRAM_CS_CONFIG_EN) == 0U) { in compute_ddr_phy()
2520 odt_rd = (regs->cs[i].config >> 20U) & U(0x7); in compute_ddr_phy()
2521 odt_wr = (regs->cs[i].config >> 16U) & U(0x7); in compute_ddr_phy()
2530 regs->sdram_cfg[0] &= ~(1 << 28U); in compute_ddr_phy()
2531 regs->sdram_cfg[1] &= ~(1 << 2U); in compute_ddr_phy()
2532 input.rcw[0] = (regs->sdram_rcw[0] >> 28U) & U(0xf); in compute_ddr_phy()
2533 input.rcw[1] = (regs->sdram_rcw[0] >> 24U) & U(0xf); in compute_ddr_phy()
2534 input.rcw[2] = (regs->sdram_rcw[0] >> 20U) & U(0xf); in compute_ddr_phy()
2535 input.rcw[3] = (regs->sdram_rcw[0] >> 16U) & U(0xf); in compute_ddr_phy()
2536 input.rcw[4] = (regs->sdram_rcw[0] >> 12U) & U(0xf); in compute_ddr_phy()
2537 input.rcw[5] = (regs->sdram_rcw[0] >> 8U) & U(0xf); in compute_ddr_phy()
2538 input.rcw[6] = (regs->sdram_rcw[0] >> 4U) & U(0xf); in compute_ddr_phy()
2539 input.rcw[7] = (regs->sdram_rcw[0] >> 0U) & U(0xf); in compute_ddr_phy()
2540 input.rcw[8] = (regs->sdram_rcw[1] >> 28U) & U(0xf); in compute_ddr_phy()
2541 input.rcw[9] = (regs->sdram_rcw[1] >> 24U) & U(0xf); in compute_ddr_phy()
2542 input.rcw[10] = (regs->sdram_rcw[1] >> 20U) & U(0xf); in compute_ddr_phy()
2543 input.rcw[11] = (regs->sdram_rcw[1] >> 16U) & U(0xf); in compute_ddr_phy()
2544 input.rcw[12] = (regs->sdram_rcw[1] >> 12U) & U(0xf); in compute_ddr_phy()
2545 input.rcw[13] = (regs->sdram_rcw[1] >> 8U) & U(0xf); in compute_ddr_phy()
2546 input.rcw[14] = (regs->sdram_rcw[1] >> 4U) & U(0xf); in compute_ddr_phy()
2547 input.rcw[15] = (regs->sdram_rcw[1] >> 0U) & U(0xf); in compute_ddr_phy()
2548 input.rcw3x = (regs->sdram_rcw[2] >> 8U) & U(0xff); in compute_ddr_phy()
2606 tcfg0 = regs->timing_cfg[0]; in compute_ddr_phy()
2607 tcfg4 = regs->timing_cfg[4]; in compute_ddr_phy()
2611 regs->timing_cfg[0] = tcfg0; in compute_ddr_phy()
2612 regs->timing_cfg[4] = tcfg4; in compute_ddr_phy()