Lines Matching refs:BIT_32
128 #define CTLR_ENABLE_G1NS_BIT BIT_32(CTLR_ENABLE_G1NS_SHIFT)
129 #define CTLR_ENABLE_G1S_BIT BIT_32(CTLR_ENABLE_G1S_SHIFT)
130 #define CTLR_ARE_S_BIT BIT_32(CTLR_ARE_S_SHIFT)
131 #define CTLR_ARE_NS_BIT BIT_32(CTLR_ARE_NS_SHIFT)
132 #define CTLR_DS_BIT BIT_32(CTLR_DS_SHIFT)
133 #define CTLR_E1NWF_BIT BIT_32(CTLR_E1NWF_SHIFT)
134 #define GICD_CTLR_RWP_BIT BIT_32(GICD_CTLR_RWP_SHIFT)
195 #define GICR_CTLR_UWP_BIT BIT_32(GICR_CTLR_UWP_SHIFT)
198 #define GICR_CTLR_RWP_BIT BIT_32(GICR_CTLR_RWP_SHIFT)
199 #define GICR_CTLR_EN_LPIS_BIT BIT_32(0)
208 #define WAKER_CA_BIT BIT_32(WAKER_CA_SHIFT)
209 #define WAKER_PS_BIT BIT_32(WAKER_PS_SHIFT)
220 #define TYPER_LAST_BIT BIT_32(TYPER_LAST_SHIFT)
237 #define ICC_SRE_EN_BIT BIT_32(3)
238 #define ICC_SRE_DIB_BIT BIT_32(2)
239 #define ICC_SRE_DFB_BIT BIT_32(1)
240 #define ICC_SRE_SRE_BIT BIT_32(0)
246 #define IGRPEN1_EL3_ENABLE_G1NS_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1NS_SHIFT)
247 #define IGRPEN1_EL3_ENABLE_G1S_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1S_SHIFT)
251 #define IGRPEN1_EL1_ENABLE_G0_BIT BIT_32(IGRPEN1_EL1_ENABLE_G0_SHIFT)
302 #define GITS_CTLR_ENABLED_BIT BIT_32(0)
303 #define GITS_CTLR_QUIESCENT_BIT BIT_32(1)