Lines Matching refs:U
34 #define STM32MP1_CHIP_ID U(0x500)
36 #define STM32MP157C_PART_NB U(0x05000000)
37 #define STM32MP157A_PART_NB U(0x05000001)
38 #define STM32MP153C_PART_NB U(0x05000024)
39 #define STM32MP153A_PART_NB U(0x05000025)
40 #define STM32MP151C_PART_NB U(0x0500002E)
41 #define STM32MP151A_PART_NB U(0x0500002F)
42 #define STM32MP157F_PART_NB U(0x05000080)
43 #define STM32MP157D_PART_NB U(0x05000081)
44 #define STM32MP153F_PART_NB U(0x050000A4)
45 #define STM32MP153D_PART_NB U(0x050000A5)
46 #define STM32MP151F_PART_NB U(0x050000AE)
47 #define STM32MP151D_PART_NB U(0x050000AF)
49 #define STM32MP1_REV_B U(0x2000)
50 #define STM32MP1_REV_Z U(0x2001)
55 #define PKG_AA_LFBGA448 U(4)
56 #define PKG_AB_LFBGA354 U(3)
57 #define PKG_AC_TFBGA361 U(2)
58 #define PKG_AD_TFBGA257 U(1)
63 #define STM32MP_ROM_BASE U(0x00000000)
64 #define STM32MP_ROM_SIZE U(0x00020000)
66 #define STM32MP_SYSRAM_BASE U(0x2FFC0000)
67 #define STM32MP_SYSRAM_SIZE U(0x00040000)
82 #define STM32MP_DDR_BASE U(0xC0000000)
83 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
85 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
86 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
88 #define STM32MP_DDR_S_SIZE U(0)
89 #define STM32MP_DDR_SHMEM_SIZE U(0)
102 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
104 #define STM32MP_HEADER_SIZE U(0x00000100)
115 #define STM32MP_BL32_SIZE U(0)
122 #define STM32MP_BL32_SIZE U(0x00012000) /* 72 KB for BL32 */
129 #define STM32MP_BL2_SIZE U(0x0001A000) /* 100 KB for BL2 */
135 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
149 #define STM32MP_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
154 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
157 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000)
162 #define STM32MP_NOR_BL33_OFFSET U(0x00080000)
164 #define STM32MP_NOR_TEEH_OFFSET U(0x00280000)
165 #define STM32MP_NOR_TEED_OFFSET U(0x002C0000)
166 #define STM32MP_NOR_TEEX_OFFSET U(0x00300000)
169 #define STM32MP_NAND_BL33_OFFSET U(0x00200000)
171 #define STM32MP_NAND_TEEH_OFFSET U(0x00600000)
172 #define STM32MP_NAND_TEED_OFFSET U(0x00680000)
173 #define STM32MP_NAND_TEEX_OFFSET U(0x00700000)
179 #define STM32MP1_DEVICE1_BASE U(0x40000000)
180 #define STM32MP1_DEVICE1_SIZE U(0x40000000)
182 #define STM32MP1_DEVICE2_BASE U(0x80000000)
183 #define STM32MP1_DEVICE2_SIZE U(0x40000000)
188 #define RCC_BASE U(0x50000000)
193 #define PWR_BASE U(0x50001000)
198 #define GPIOA_BASE U(0x50002000)
199 #define GPIOB_BASE U(0x50003000)
200 #define GPIOC_BASE U(0x50004000)
201 #define GPIOD_BASE U(0x50005000)
202 #define GPIOE_BASE U(0x50006000)
203 #define GPIOF_BASE U(0x50007000)
204 #define GPIOG_BASE U(0x50008000)
205 #define GPIOH_BASE U(0x50009000)
206 #define GPIOI_BASE U(0x5000A000)
207 #define GPIOJ_BASE U(0x5000B000)
208 #define GPIOK_BASE U(0x5000C000)
209 #define GPIOZ_BASE U(0x54004000)
210 #define GPIO_BANK_OFFSET U(0x1000)
213 #define GPIO_BANK_A U(0)
214 #define GPIO_BANK_B U(1)
215 #define GPIO_BANK_C U(2)
216 #define GPIO_BANK_D U(3)
217 #define GPIO_BANK_E U(4)
218 #define GPIO_BANK_F U(5)
219 #define GPIO_BANK_G U(6)
220 #define GPIO_BANK_H U(7)
221 #define GPIO_BANK_I U(8)
222 #define GPIO_BANK_J U(9)
223 #define GPIO_BANK_K U(10)
224 #define GPIO_BANK_Z U(25)
231 #define USART1_BASE U(0x5C000000)
232 #define USART2_BASE U(0x4000E000)
233 #define USART3_BASE U(0x4000F000)
234 #define UART4_BASE U(0x40010000)
235 #define UART5_BASE U(0x40011000)
236 #define USART6_BASE U(0x44003000)
237 #define UART7_BASE U(0x40018000)
238 #define UART8_BASE U(0x40019000)
239 #define STM32MP_UART_BAUDRATE U(115200)
258 #define STM32MP1_ETZPC_BASE U(0x5C007000)
261 #define STM32MP1_ETZPC_TZMA_ROM U(0)
262 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1)
356 #define STM32MP1_TZC_BASE U(0x5C006000)
358 #define STM32MP1_TZC_A7_ID U(0)
359 #define STM32MP1_TZC_M4_ID U(1)
360 #define STM32MP1_TZC_LCD_ID U(3)
361 #define STM32MP1_TZC_GPU_ID U(4)
362 #define STM32MP1_TZC_MDMA_ID U(5)
363 #define STM32MP1_TZC_DMA_ID U(6)
364 #define STM32MP1_TZC_USB_HOST_ID U(7)
365 #define STM32MP1_TZC_USB_OTG_ID U(8)
366 #define STM32MP1_TZC_SDMMC_ID U(9)
367 #define STM32MP1_TZC_ETH_ID U(10)
368 #define STM32MP1_TZC_DAP_ID U(15)
376 #define STM32MP_SDMMC1_BASE U(0x58005000)
377 #define STM32MP_SDMMC2_BASE U(0x58007000)
378 #define STM32MP_SDMMC3_BASE U(0x48004000)
380 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
381 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
382 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
383 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
384 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
395 #define DATA0_OTP U(0)
396 #define PART_NUMBER_OTP U(1)
397 #define NAND_OTP U(9)
398 #define PACKAGE_OTP U(16)
399 #define HW2_OTP U(18)
414 #define HW2_OTP_IWDG_HW_POS U(3)
415 #define HW2_OTP_IWDG_FZ_STOP_POS U(5)
416 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7)
428 #define NAND_PAGE_SIZE_2K U(0)
429 #define NAND_PAGE_SIZE_4K U(1)
430 #define NAND_PAGE_SIZE_8K U(2)
435 #define NAND_BLOCK_SIZE_64_PAGES U(0)
436 #define NAND_BLOCK_SIZE_128_PAGES U(1)
437 #define NAND_BLOCK_SIZE_256_PAGES U(2)
442 #define NAND_BLOCK_NB_UNIT U(256)
451 #define NAND_ECC_BIT_NB_UNSET U(0)
452 #define NAND_ECC_BIT_NB_1_BITS U(1)
453 #define NAND_ECC_BIT_NB_4_BITS U(2)
454 #define NAND_ECC_BIT_NB_8_BITS U(3)
455 #define NAND_ECC_ON_DIE U(4)
463 #define TAMP_BASE U(0x5C00A000)
464 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
476 #define DDRCTRL_BASE U(0x5A003000)
481 #define DDRPHYC_BASE U(0x5A004000)
486 #define IWDG_MAX_INSTANCE U(2)
487 #define IWDG1_INST U(0)
488 #define IWDG2_INST U(1)
490 #define IWDG1_BASE U(0x5C003000)
491 #define IWDG2_BASE U(0x5A002000)
496 #define BSEC_BASE U(0x5C005000)
497 #define CRYP1_BASE U(0x54001000)
498 #define DBGMCU_BASE U(0x50081000)
499 #define HASH1_BASE U(0x54002000)
500 #define I2C4_BASE U(0x5C002000)
501 #define I2C6_BASE U(0x5c009000)
502 #define RNG1_BASE U(0x54003000)
503 #define RTC_BASE U(0x5c004000)
504 #define SPI6_BASE U(0x5c001000)
505 #define STGEN_BASE U(0x5c008000)
506 #define SYSCFG_BASE U(0x50020000)