Lines Matching refs:priority

4490 …_PAYLOAD\_BASE}}. If both are defined, \sphinxcode{\sphinxupquote{EL3\_PAYLOAD\_BASE}} has priority
7841 Configure the priority mask register to allow interrupts of all priorities
8027 This macro must be defined to the EL3 exception priority level associated with
8029 (therefore of lower priority) than \sphinxcode{\sphinxupquote{PLAT\_SDEI\_CRITICAL\_PRI}}.
8035 This macro must be defined to the EL3 exception priority level associated with
8037 (therefore of higher priority) than \sphinxcode{\sphinxupquote{PLAT\_SDEI\_NORMAL\_PRI}}.
8041 …f[\detokenize{glossary:term-SDEI}]{\sphinxtermref{\DUrole{xref,std,std-term}{SDEI}}}} priority must
8042 …erref[\detokenize{glossary:term-SDEI}]{\sphinxtermref{\DUrole{xref,std,std-term}{SDEI}}}} priority.
8723 This API returns the type of the highest priority pending interrupt at the
8784 This API returns the id of the highest priority pending interrupt at the
8861 priority pending interrupt from pending to active in the interrupt controller.
14856 is based on a priority scheme. This priority scheme is closely tied to how the
14861 …components/exception-handling:partitioning-priority-levels}]{\sphinxcrossref{partition}}} the Secu…
14862 priority levels as applicable for the Secure software stack. It then assigns the
14863 dispatchers to one or more priority levels. The dispatchers then register
14864 handlers for the priority levels at runtime. A dispatcher can register handlers
14865 for more than one priority level.
14870 A priority level is \sphinxstyleemphasis{active} when a handler at that priority level is currently
14873 priority of the acknowledged interrupt is used to match its registered handler.
14874 The priority level is likewise implicitly deactivated when the interrupt
14878 Non\sphinxhyphen{}interrupt exceptions (SErrors, for example) don’t have a notion of priority.
14879 In order for the priority arbitration to work, the {\hyperref[\detokenize{glossary:term-EHF}]{\sphi…
14880 for these non\sphinxhyphen{}interrupt exceptions to assume a priority, and to interwork with
14882 activate and deactivate the respective priority level as and when they’re
14886 Because priority activation and deactivation for interrupt handling is implicit
14887 and involves GIC priority masking, it’s impossible for a lower priority
14888 interrupt to preempt a higher priority one. By extension, this means that a
14889 lower priority dispatcher cannot preempt a higher\sphinxhyphen{}priority one. Priority
14891 …ermref{\DUrole{xref,std,std-term}{EHF}}}} therefore disallows for lower priority level to be activ…
14892 whilst a higher priority level is active, and would result in a panic.
14893 Likewise, a panic would result if it’s attempted to deactivate a lower priority
14894 level when a higher priority level is active.
14897 In essence, priority level activation and deactivation conceptually works like a
14898 stack—priority levels stack up in strictly increasing fashion, and need to be
14901 …ize{components/exception-handling:transition-of-priority-levels}]{\sphinxcrossref{Transition of pr…
14915 sufficient priority are signalled as FIQs, and therefore will be routed to
14934 lowest Secure priority. This means that no Non\sphinxhyphen{}secure interrupts can preempt
14941 interrupts into distinct priority levels. A dispatcher that chooses to receive
14942 interrupts can then \sphinxstyleemphasis{own} one or more priority levels, and register interrupt
14943 handlers for them. A given priority level can be assigned to only one handler. A
14944 dispatcher may register more than one priority level.
14947 Dispatchers are assigned interrupt priority levels in two steps:
14950 \subsubsection{Partitioning priority levels}
14951 \label{\detokenize{components/exception-handling:partitioning-priority-levels}}\label{\detokenize{c…
14954 interrupts to a priority level. In other words, all interrupts that are to
14955 target a particular dispatcher should fall in a particular priority level. For
14956 priority assignment:
14960 Of the 8 bits of priority that Arm GIC architecture permits, bit 7 must be 0
14969 6 and 5), the platform can partition into 4 secure priority ranges: \sphinxcode{\sphinxupquote{0x0}…
14977 security states must implement at least 32 priority levels; i.e., at least 5
14979 choosing \sphinxstyleemphasis{n} bits for priority range assignment, the platform must ensure
14980 that at least \sphinxcode{\sphinxupquote{n+1}} top bits of GIC priority are writeable.
14984 The priority thus assigned to an interrupt is also used to determine the
14985 priority of delegated execution in lower ELs. Delegated execution in lower EL is
14986 associated with a priority level chosen with \sphinxcode{\sphinxupquote{ehf\_activate\_priority()}}…
14987 …nts/exception-handling:ehf-apis}]{\sphinxcrossref{later}}}). The chosen priority level also determ…
14992 The platform expresses the chosen priority levels by declaring an array of
14993 priority level descriptors. Each entry in the array is of type
14994 \sphinxcode{\sphinxupquote{ehf\_pri\_desc\_t}}, and declares a priority level, and shall be populat…
15015 \subsubsection{Programming priority}
15016 \label{\detokenize{components/exception-handling:programming-priority}}
15018 …enize{components/exception-handling:partitioning-priority-levels}]{\sphinxcrossref{Partitioning pr…
15019 expresses the required levels of priority. It however doesn’t choose interrupts
15020 nor program the required priority in GIC.
15026 priority of secure interrupts must match that as determined in the
15027 …enize{components/exception-handling:partitioning-priority-levels}]{\sphinxcrossref{Partitioning pr…
15037 Dispatchers register handlers for their priority levels through the following
15041 \PYG{k+kt}{int}\PYG{+w}{ }\PYG{n}{ehf\PYGZus{}register\PYGZus{}priority\PYGZus{}handler}\PYG{p}{(}\…
15049 The priority level for which the handler is being registered;
15058 If a dispatcher owns more than one priority levels, it has to call the API for
15066 There exists a descriptor with the priority level requested.
15090 example, expects the platform to allocate two different priority levels—
15125 \PYG{c+cm}{/* Install priority level descriptors for each dispatcher */}
15132 \PYG{c+cm}{/* Expose priority descriptors to Exception Handling Framework */}
15140 … Dispatcher 1 owns interrupts d1\PYGZus{}0 and d1\PYGZus{}1, so assigns priority DISP1\PYGZus{}PRI…
15144 … Dispatcher 2 owns interrupts d2\PYGZus{}0 and d2\PYGZus{}1, so assigns priority DISP2\PYGZus{}PRI…
15148 … Dispatcher 3 owns interrupts d3\PYGZus{}0 and d3\PYGZus{}1, so assigns priority DISP3\PYGZus{}PRI…
15156 \PYG{n}{ehf\PYGZus{}register\PYGZus{}priority\PYGZus{}handler}\PYG{p}{(}\PYG{n}{DISP1\PYGZus{}PRIO}…
15159 \PYG{n}{ehf\PYGZus{}register\PYGZus{}priority\PYGZus{}handler}\PYG{p}{(}\PYG{n}{DISP2\PYGZus{}PRIO}…
15162 \PYG{n}{ehf\PYGZus{}register\PYGZus{}priority\PYGZus{}handler}\PYG{p}{(}\PYG{n}{DISP3\PYGZus{}PRIO}…
15174 A priority level is said to be \sphinxstyleemphasis{active} when an exception of that priority is
15182 of the exception, the corresponding priority level ought to be deactivated. As
15195 priority level before returning to the {\hyperref[\detokenize{glossary:term-EHF}]{\sphinxtermref{\D…
15238 \sphinxcode{\sphinxupquote{ehf\_activate\_priority()}} activates the supplied priority level, but o…
15239 if the current active priority is higher than the given one; otherwise
15241 priority, the {\hyperref[\detokenize{glossary:term-EHF}]{\sphinxtermref{\DUrole{xref,std,std-term}{…
15242 the PE to the priority being activated.  Dispatchers typically only need to
15244 delegate execution to a lower EL at a desired priority level.
15248 \sphinxcode{\sphinxupquote{ehf\_deactivate\_priority()}} deactivates a given priority, but only if …
15249 current active priority is equal to the given one; otherwise panics. {\hyperref[\detokenize{glossar…
15251 priority before the call to \sphinxcode{\sphinxupquote{ehf\_activate\_priority()}}. Dispatchers
15258 …owed {\hyperref[\detokenize{components/exception-handling:transition-of-priority-levels}]{\sphinxc…
15262 \subsection{Transition of priority levels}
15263 \label{\detokenize{components/exception-handling:transition-of-priority-levels}}
15266 be called to transition the current priority level on a PE. A given sequence of
15271 …}]{\sphinxtermref{\DUrole{xref,std,std-term}{EHF}}}} only allows for the priority to increase (i.e.
15276 …}]{\sphinxtermref{\DUrole{xref,std,std-term}{EHF}}}} only allows for the priority to decrease (i.e.
15277 numeric value increases). Additionally, the priority being deactivated is
15278 required to be the current priority.
15291 delegated execution thereafter, has the effect of raising GIC’s priority
15310 …emphasis{Yielding} SMCs carry the semantics of a preemptible, lower\sphinxhyphen{}priority request.
15368 Platform assigns priorities by installing priority level descriptors for
15369 …enize{components/exception-handling:partitioning-priority-levels}]{\sphinxcrossref{Partitioning pr…
15374 …detokenize{components/exception-handling:programming-priority}]{\sphinxcrossref{Programming priori…
15396 …detokenize{components/exception-handling:programming-priority}]{\sphinxcrossref{Programming priori…
15397 interrupts. This programs the appropriate priority and group (Group 0) on
15419 …erm}{EHF}}}} programs the \sphinxstyleemphasis{Priority Mask Register} of the PE to the priority of
15424 …term-EHF}]{\sphinxtermref{\DUrole{xref,std,std-term}{EHF}}}} marks that priority level \sphinxstyl…
15430 \sphinxstyleemphasis{deactivate} the priority level before returning to the {\hyperref[\detokenize{…
15451 priority level. This also has the effect of raising GIC priority mask, thus
15452 preventing interrupts of lower priority from preempting the handling. The
15459 \sphinxcode{\sphinxupquote{ehf\_deactivate\_priority()}} to deactivate the priority level activated
15460 earlier. This also has the effect of lowering GIC priority mask to what it
15469 The GIC priority scheme, by design, prioritises Secure interrupts over Normal
15474 …enize{components/exception-handling:partitioning-priority-levels}]{\sphinxcrossref{Partitioning pr…
15475 dispatchers fall in distinct priority levels. Because they’re routed via the
15478 in \sphinxstyleemphasis{Active} state), only interrupts of higher priority are signalled to the PE,
15479 even if interrupts of same or lower priority are pending. This has the side
15481 dispatcher handling its (higher priority) interrupts.
15486 into runtime firmware. The platform should sensibly delineate priority to
15488 critical nature (RAS, for example) should be assigned higher priority than
15489 …tokenize{glossary:term-SDEI}]{\sphinxtermref{\DUrole{xref,std,std-term}{SDEI}}}}, Critical priority
15490 …inxtermref{\DUrole{xref,std,std-term}{SDEI}}}} should be assigned higher priority than Normal ones.
15501 priority scheme, the size of descriptor array exposed with
15508 The platform must ensure that the priority assigned to the dispatcher in the
15509 exception descriptor and the programmed priority of interrupts handled by the
16821 …latform-interrupt-controller-API:function-unsigned-int-plat-ic-get-running-priority-void-optional}}
16828 This API should return the priority of the interrupt the PE is currently
16834 is read to determine the priority of the interrupt.
16930 …n: void plat\_ic\_set\_interrupt\_priority(unsigned int id, unsigned int priority); {[}optional{]}}
16931 …t-controller-API:function-void-plat-ic-set-interrupt-priority-unsigned-int-id-unsigned-int-priorit…
16939 This API should set the priority of the interrupt specified by first parameter
16940 …\sphinxupquote{id}} to the value set by the second parameter \sphinxcode{\sphinxupquote{priority}}.
16944 writes to GIC \sphinxstyleemphasis{Priority Register} set interrupt priority.
17158 …nts/platform-interrupt-controller-API:function-unsigned-int-plat-ic-set-priority-mask-unsigned-int…
17165 This API should set the priority mask (first parameter) in the interrupt
17166 controller such that only interrupts of higher priority than the supplied one
17167 may be signalled to the PE. The API should return the current priority value
17492 …e{components/exception-handling:partitioning-priority-levels}]{\sphinxcrossref{\DUrole{std,std-ref…
17493 the macro \sphinxcode{\sphinxupquote{PLAT\_RAS\_PRI}} to the priority level used for RAS exceptions.
17494 Platforms would typically want to allocate the highest secure priority for
17499 documentation. I.e., for interrupts, the priority management is implicit; but
17831 Event priority: \sphinxcode{\sphinxupquote{SDEI\_MAPF\_CRITICAL}} or \sphinxcode{\sphinxupquote{SDE…
17916 …uote{SDEI\_MAPF\_NORMAL}}: Marks the event as having \sphinxstyleemphasis{Normal} priority. This is
17917 the default priority.
17921 …xupquote{SDEI\_MAPF\_CRITICAL}}: Marks the event as having \sphinxstyleemphasis{Critical} priority.
17968 Install priority descriptors for Normal and Critical SDEI interrupts.
18094 The priority of the event (either Critical or Normal, as configured by the
18095 platform at build\sphinxhyphen{}time) shouldn’t cause priority inversion. This means:
18099 If it’s of Normal priority, neither Normal nor Critical priority dispatch
18104 If it’s of a Critical priority, no Critical priority dispatch must be
18124 priority so as not to cause priority level inversion within Exception
20246 implemented by SPMC to perform priority drop and interrupt deactivation (we
20247 assume EOImode = 0, i.e. priority drop and deactivation are done together).
22910 Interrupt priority value
28963 (priority, group, configuration). Each element of the array shall be populated
28972 8\sphinxhyphen{}bit interrupt priority,
31121 enable the secure interrupts, ensure that their priority is always higher than
31727 another higher priority Secure\sphinxhyphen{}EL1 interrupt or a EL3 interrupt. The SPD
31860 \sphinxcode{\sphinxupquote{yielding}} SMC processing or by a higher priority EL3 interrupt during
32015 that means that a higher priority interrupt has preempted it. Invoke
60921 gic: Remove ‘lowest priority’ constants
60925 should define these if required, or instead determine the correct priority
61049 non\sphinxhyphen{}secure world, and may have higher priority than secure world interrupts.