Lines Matching refs:security
36 Secure-EL1 depending upon the security state of the current execution
40 Secure-EL1, Non-secure EL1 or EL2 depending upon the security state of the
45 depending upon the security state of the current execution context. It is
66 FEL. This register is configured independently by EL3 software for each security
67 state prior to entry into a lower exception level in that security state.
70 its target exception level for each security state. It is represented by a
71 single bit for each security state. A value of ``0`` means that the interrupt
76 either security state.
174 FIQ or IRQ signal to the CPU depending upon the current security state. The
183 This applies when execution is in either security state.
190 particular security state, then interrupt signal will be routed to EL3 when in
191 that security state. This means that all the other interrupt types using the
250 security state.
264 security state. EL3 interrupts are not considered.
280 Switching execution between the two security states is a requirement for
324 #. Security state, bit[0]. This bit indicates the security state of the lower
334 for the security state specified in the ``flags`` parameter.
338 ``cpu_context`` structure of the current CPU for the target security state. On
370 prior to entry into a lower exception level in either security state. The
372 each security state in the ``cpu_context`` structure of each CPU. It exports the
374 model for each security state for the current CPU. The value of ``SCR_EL3`` stored
386 security state of the current CPU. ``cm_write_scr_el3_bit()`` writes a ``0`` or ``1``
434 either security state i.e **CSS=0, TEL3=0** & **CSS=1, TEL3=0** for
525 is used to generate non-secure interrupts in either security state.
671 with the current security state and a reference to the ``cpu_context_t``
672 structure for the current security state are passed to the handler function
676 structure for the target security state.
679 the security state determined by the handler routine. The ``el3_exit()``
681 ``cpu_context_t`` data structure for the target security state.
695 service during registration. It should use the security state of the
706 could use the security state flag to check this.
710 if the security state of the execution context where the interrupt was
711 generated is not the same as the security state required for handling
722 security state. It must then restore the system register context of the
723 target security state. It should use the ``cm_set_next_eret_context()`` API
725 security state.
752 exception level and the security state from where the Secure-EL1 interrupt was
765 #. It uses the security state provided in the ``flags`` parameter to ensure
919 security state where the interrupt was originally taken from. The SP should use