Lines Matching refs:address
30 address" for more information.
32 Programmable CPU reset address
35 By default, TF-A assumes that the CPU reset address is not programmable.
36 Therefore, all CPUs start at the same address (typically address 0) whenever
40 If the reset vector address (reflected in the reset vector base address register
42 at the right address, both on a cold and warm reset. Therefore, the boot type
45 |Reset code flow with programmable reset address|
51 On both the FVP and Juno platforms, the reset vector address is not programmable
77 Programmable CPU reset address, Cold boot on a single CPU
81 a programmable CPU reset address and which release a single CPU out of reset.
85 |Reset code flow with programmable reset address and single CPU released out of reset|
91 Using BL31 entrypoint as the reset address
104 BL31 is loaded to its runtime address, which must match the CPU's ``RVBAR_EL3``
105 reset vector base address, before the application processor is powered on.
111 address dynamically at run-time, it is possible to set the initial value of the
116 which case the ``bl31.bin`` image must be loaded to its run address in Trusted
118 address. See the :ref:`Arm Fixed Virtual Platforms (FVP)` for details of running
121 Although technically it would be possible to program the reset base address with
151 initialisation, for example programming a TrustZone address space controller.
159 .. |Reset code flow with programmable reset address| image:: ../resources/diagrams/reset_code_no_bo…
161 .. |Reset code flow with programmable reset address and single CPU released out of reset| image:: .…