Lines Matching refs:base_addr
65 int console_imx_uart_core_init(uintptr_t base_addr, unsigned int uart_clk, in console_imx_uart_core_init() argument
72 write_reg(base_addr, IMX_UART_CR2_OFFSET, 0); in console_imx_uart_core_init()
74 val = read_reg(base_addr, IMX_UART_CR2_OFFSET); in console_imx_uart_core_init()
78 write_reg(base_addr, IMX_UART_CR1_OFFSET, IMX_UART_CR1_UARTEN); in console_imx_uart_core_init()
83 write_reg(base_addr, IMX_UART_CR2_OFFSET, val); in console_imx_uart_core_init()
87 write_reg(base_addr, IMX_UART_CR3_OFFSET, val); in console_imx_uart_core_init()
90 write_reg(base_addr, IMX_UART_CR4_OFFSET, 0x8000); in console_imx_uart_core_init()
99 write_reg(base_addr, IMX_UART_FCR_OFFSET, val); in console_imx_uart_core_init()
115 write_reg(base_addr, IMX_UART_BIR_OFFSET, 0x0f); in console_imx_uart_core_init()
117 write_reg(base_addr, IMX_UART_BMR_OFFSET, val); in console_imx_uart_core_init()
132 int console_imx_uart_core_putc(int c, uintptr_t base_addr) in console_imx_uart_core_putc() argument
137 console_imx_uart_core_putc('\r', base_addr); in console_imx_uart_core_putc()
140 write_reg(base_addr, IMX_UART_TXD_OFFSET, c); in console_imx_uart_core_putc()
144 val = read_reg(base_addr, IMX_UART_STAT2_OFFSET); in console_imx_uart_core_putc()
158 int console_imx_uart_core_getc(uintptr_t base_addr) in console_imx_uart_core_getc() argument
162 val = read_reg(base_addr, IMX_UART_TS_OFFSET); in console_imx_uart_core_getc()
166 val = read_reg(base_addr, IMX_UART_RXD_OFFSET); in console_imx_uart_core_getc()
178 void console_imx_uart_core_flush(uintptr_t base_addr) in console_imx_uart_core_flush() argument