Lines Matching refs:ap_index
70 static void dump_ccu(int ap_index) in dump_ccu() argument
80 win_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); in dump_ccu()
84 alr = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, in dump_ccu()
86 ahr = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_index, in dump_ccu()
94 win_cr = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_index)); in dump_ccu()
117 int ccu_is_win_enabled(int ap_index, uint32_t win_id) in ccu_is_win_enabled() argument
119 return mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)) & in ccu_is_win_enabled()
123 void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id) in ccu_enable_win() argument
138 mmio_write_32(CCU_WIN_ALR_OFFSET(ap_index, win_id), alr); in ccu_enable_win()
139 mmio_write_32(CCU_WIN_AHR_OFFSET(ap_index, win_id), ahr); in ccu_enable_win()
144 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), ccu_win_reg); in ccu_enable_win()
147 static void ccu_disable_win(int ap_index, uint32_t win_id) in ccu_disable_win() argument
156 win_reg = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); in ccu_disable_win()
158 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), win_reg); in ccu_disable_win()
169 void ccu_temp_win_insert(int ap_index, struct addr_map_win *win, int size) in ccu_temp_win_insert() argument
176 ccu_enable_win(ap_index, win, win_id); in ccu_temp_win_insert()
185 void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size) in ccu_temp_win_remove() argument
195 target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); in ccu_temp_win_remove()
199 base = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, win_id)); in ccu_temp_win_remove()
207 ccu_disable_win(ap_index, win_id); in ccu_temp_win_remove()
218 static uint32_t ccu_dram_target_get(int ap_index) in ccu_dram_target_get() argument
225 const uint32_t win_id = (ap_index == 0) ? 2 : 1; in ccu_dram_target_get()
228 target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); in ccu_dram_target_get()
235 void ccu_dram_target_set(int ap_index, uint32_t target) in ccu_dram_target_set() argument
242 const uint32_t win_id = (ap_index == 0) ? 2 : 1; in ccu_dram_target_set()
245 dram_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); in ccu_dram_target_set()
248 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), dram_cr); in ccu_dram_target_set()
252 void ccu_dram_win_config(int ap_index, struct addr_map_win *win) in ccu_dram_win_config() argument
259 const uint32_t win_id = (ap_index == 0) ? 2 : 1; in ccu_dram_win_config()
269 ccu_disable_win(ap_index, win_id); in ccu_dram_win_config()
271 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), in ccu_dram_win_config()
274 ccu_enable_win(ap_index, win, win_id); in ccu_dram_win_config()
317 int init_ccu(int ap_index) in init_ccu() argument
335 marvell_get_ccu_memory_map(ap_index, &win, &win_count); in init_ccu()
350 dram_target = ccu_dram_target_get(ap_index); in init_ccu()
352 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); in init_ccu()
371 ccu_disable_win(ap_index, win_id); in init_ccu()
373 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), in init_ccu()
384 ccu_enable_win(ap_index, win, win_id); in init_ccu()
390 win_reg = (marvell_get_ccu_gcr_target(ap_index) & CCU_GCR_TARGET_MASK) in init_ccu()
392 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); in init_ccu()
395 dump_ccu(ap_index); in init_ccu()