Lines Matching refs:mci_index
22 #define MCI_WRITE_READ_DATA_REG(mci_index) \ argument
23 MVEBU_MCI_REG_BASE_REMAP(mci_index)
27 #define MCI_ACCESS_CMD_REG(mci_index) \ argument
28 (MVEBU_MCI_REG_BASE_REMAP(mci_index) + 0x4)
292 static int mci_poll_command_completion(int mci_index, int command_type) in mci_poll_command_completion() argument
305 mci_cmd_value = mci_mmio_read_32(MCI_ACCESS_CMD_REG(mci_index)); in mci_poll_command_completion()
343 static int mci_axi_set_pcie_mode(int mci_index) in mci_axi_set_pcie_mode() argument
353 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), in mci_axi_set_pcie_mode()
358 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_axi_set_pcie_mode()
366 if (mci_poll_command_completion(mci_index, MCI_CMD_WRITE) == 0) { in mci_axi_set_pcie_mode()
368 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_axi_set_pcie_mode()
375 if (mci_poll_command_completion(mci_index, MCI_CMD_READ) == 0) { in mci_axi_set_pcie_mode()
377 MCI_WRITE_READ_DATA_REG(mci_index)); in mci_axi_set_pcie_mode()
388 static int mci_axi_set_fifo_thresh(int mci_index) in mci_axi_set_fifo_thresh() argument
406 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data); in mci_axi_set_fifo_thresh()
407 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_axi_set_fifo_thresh()
410 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_axi_set_fifo_thresh()
413 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), in mci_axi_set_fifo_thresh()
416 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_axi_set_fifo_thresh()
420 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_axi_set_fifo_thresh()
427 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data); in mci_axi_set_fifo_thresh()
428 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_axi_set_fifo_thresh()
431 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_axi_set_fifo_thresh()
438 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data); in mci_axi_set_fifo_thresh()
439 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_axi_set_fifo_thresh()
442 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_axi_set_fifo_thresh()
445 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), in mci_axi_set_fifo_thresh()
447 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_axi_set_fifo_thresh()
451 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_axi_set_fifo_thresh()
457 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data); in mci_axi_set_fifo_thresh()
458 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_axi_set_fifo_thresh()
462 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_axi_set_fifo_thresh()
475 static int mci_axi_set_fifo_rx_tx_thresh(int mci_index) in mci_axi_set_fifo_rx_tx_thresh() argument
481 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), in mci_axi_set_fifo_rx_tx_thresh()
483 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_axi_set_fifo_rx_tx_thresh()
487 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_axi_set_fifo_rx_tx_thresh()
490 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), in mci_axi_set_fifo_rx_tx_thresh()
492 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_axi_set_fifo_rx_tx_thresh()
496 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_axi_set_fifo_rx_tx_thresh()
499 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), in mci_axi_set_fifo_rx_tx_thresh()
502 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_axi_set_fifo_rx_tx_thresh()
506 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_axi_set_fifo_rx_tx_thresh()
509 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), in mci_axi_set_fifo_rx_tx_thresh()
511 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_axi_set_fifo_rx_tx_thresh()
515 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_axi_set_fifo_rx_tx_thresh()
518 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), in mci_axi_set_fifo_rx_tx_thresh()
520 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_axi_set_fifo_rx_tx_thresh()
524 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_axi_set_fifo_rx_tx_thresh()
527 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), in mci_axi_set_fifo_rx_tx_thresh()
529 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_axi_set_fifo_rx_tx_thresh()
533 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_axi_set_fifo_rx_tx_thresh()
536 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), in mci_axi_set_fifo_rx_tx_thresh()
540 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_axi_set_fifo_rx_tx_thresh()
545 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_axi_set_fifo_rx_tx_thresh()
548 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), in mci_axi_set_fifo_rx_tx_thresh()
552 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_axi_set_fifo_rx_tx_thresh()
557 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_axi_set_fifo_rx_tx_thresh()
568 static int mci_enable_simultaneous_transactions(int mci_index) in mci_enable_simultaneous_transactions() argument
574 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), in mci_enable_simultaneous_transactions()
578 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_enable_simultaneous_transactions()
582 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_enable_simultaneous_transactions()
585 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), in mci_enable_simultaneous_transactions()
588 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_enable_simultaneous_transactions()
593 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_enable_simultaneous_transactions()
596 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), in mci_enable_simultaneous_transactions()
599 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_enable_simultaneous_transactions()
604 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_enable_simultaneous_transactions()
610 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), 0xffffffff); in mci_enable_simultaneous_transactions()
611 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_enable_simultaneous_transactions()
616 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_enable_simultaneous_transactions()
622 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), 0xffffffff); in mci_enable_simultaneous_transactions()
623 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_enable_simultaneous_transactions()
628 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); in mci_enable_simultaneous_transactions()
647 static _Bool mci_simulatenous_trans_missing(int mci_index) in mci_simulatenous_trans_missing() argument
656 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), in mci_simulatenous_trans_missing()
662 ret = mci_poll_command_completion(mci_index, MCI_CMD_READ); in mci_simulatenous_trans_missing()
664 reg = mci_mmio_read_32(MCI_WRITE_READ_DATA_REG(mci_index)); in mci_simulatenous_trans_missing()
690 int mci_configure(int mci_index) in mci_configure() argument
699 if (mci_simulatenous_trans_missing(mci_index)) { in mci_configure()
701 mci_index); in mci_configure()
705 rval = mci_enable_simultaneous_transactions(mci_index); in mci_configure()
712 rval = mci_axi_set_pcie_mode(mci_index); in mci_configure()
717 rval = mci_axi_set_fifo_thresh(mci_index); in mci_configure()
722 rval = mci_axi_set_fifo_rx_tx_thresh(mci_index); in mci_configure()
823 int mci_link_tune(int mci_index) in mci_link_tune() argument
828 INFO("MCI%d initialization:\n", mci_index); in mci_link_tune()
830 ret = mci_configure(mci_index); in mci_link_tune()