Lines Matching refs:reg
64 uint32_t reg; in armada_ap806_thermal_read() local
66 reg = mmio_read_32(TSEN_STATUS); in armada_ap806_thermal_read()
68 reg = ((reg & TSEN_STATUS_TEMP_OUT_MASK) >> in armada_ap806_thermal_read()
76 if (reg >= THERMAL_SEN_OUTPUT_MSB) in armada_ap806_thermal_read()
77 reg -= THERMAL_SEN_OUTPUT_COMP; in armada_ap806_thermal_read()
79 *temp = ((COEF_M * ((signed int)reg)) - COEF_B); in armada_ap806_thermal_read()
90 uint32_t reg; in armada_ap806_thermal_overheat_irq_init() local
93 reg = mmio_read_32(DFX_IRQ_CAUSE_REG); in armada_ap806_thermal_overheat_irq_init()
96 reg = mmio_read_32(DFX_IRQ_MASK_REG); in armada_ap806_thermal_overheat_irq_init()
97 reg |= DFX_IRQ_TSEN_OVERHEAT_OFFSET; in armada_ap806_thermal_overheat_irq_init()
98 mmio_write_32(DFX_IRQ_MASK_REG, reg); in armada_ap806_thermal_overheat_irq_init()
101 reg = mmio_read_32(DFX_SERVER_IRQ_SUM_MASK_REG); in armada_ap806_thermal_overheat_irq_init()
102 reg |= DFX_SERVER_IRQ_EN; in armada_ap806_thermal_overheat_irq_init()
103 mmio_write_32(DFX_SERVER_IRQ_SUM_MASK_REG, reg); in armada_ap806_thermal_overheat_irq_init()
106 reg = mmio_read_32(TSEN_CTRL1); in armada_ap806_thermal_overheat_irq_init()
107 reg |= TSEN_CTRL1_INT_EN; in armada_ap806_thermal_overheat_irq_init()
108 mmio_write_32(TSEN_CTRL1, reg); in armada_ap806_thermal_overheat_irq_init()
198 uint32_t reg; in armada_ap806_thermal_init() local
200 reg = mmio_read_32(TSEN_CTRL0); in armada_ap806_thermal_init()
201 reg &= ~TSEN_CTRL0_RESET; in armada_ap806_thermal_init()
202 reg |= TSEN_CTRL0_START | TSEN_CTRL0_ENABLE; in armada_ap806_thermal_init()
205 reg |= TSEN_CTRL0_OSR_MAX << TSEN_CTRL0_OSR_SHIFT; in armada_ap806_thermal_init()
208 reg &= ~TSEN_CTRL0_AVG_BYPASS; in armada_ap806_thermal_init()
210 mmio_write_32(TSEN_CTRL0, reg); in armada_ap806_thermal_init()