Lines Matching refs:fspi_readl
42 static uint32_t fspi_readl(uint32_t x_addr) in fspi_readl() function
51 ui_reg = fspi_readl(FSPI_MCR0); in fspi_MDIS()
64 VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR)); in fspi_lock_LUT()
66 VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR)); in fspi_lock_LUT()
72 VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR)); in fspi_unlock_LUT()
74 VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR)); in fspi_unlock_LUT()
195 reg = fspi_readl(FSPI_MCR0); in fspi_ahb_invalidate()
198 while ((fspi_readl(FSPI_MCR0) & FSPI_MCR0_SWRST) != 0) in fspi_ahb_invalidate()
222 INFO("xAhbcr=0x%x\n", fspi_readl(FSPI_AHBCR)); in fspi_init_ahb()
225 x_flash_cr2 = fspi_readl(FSPI_FLSHA1CR2); in fspi_init_ahb()
235 x_flash_cr2 = fspi_readl(FSPI_FLSHA1CR2); in fspi_init_ahb()
296 PRA("0x%x", fspi_readl(FSPI_INTR)); in xspi_ip_read()
310 PRA("0x%x", fspi_readl(FSPI_IPCR0)); in xspi_ip_read()
320 PRA("0x%x", fspi_readl(FSPI_IPCR1)); in xspi_ip_read()
323 sts0 = fspi_readl(FSPI_STS0); in xspi_ip_read()
329 PRA("0x%x", fspi_readl(FSPI_IPCMD)); in xspi_ip_read()
331 intr = fspi_readl(FSPI_INTR); in xspi_ip_read()
340 if ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPRXWA_MASK) == 0) { in xspi_ip_read()
341 PRA("0x%x", fspi_readl(FSPI_INTR)); in xspi_ip_read()
344 while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPRXWA_MASK)) { in xspi_ip_read()
345 PRA("0x%x", fspi_readl(FSPI_INTR)); in xspi_ip_read()
351 data = fspi_readl(FSPI_RFDR + j); in xspi_ip_read()
367 while (!(fspi_readl(FSPI_IPRXFSTS) & FSPI_IPRXFSTS_FILL_MASK)) { in xspi_ip_read()
368 PRA("0x%x", fspi_readl(FSPI_IPRXFSTS)); in xspi_ip_read()
375 data = fspi_readl(FSPI_RFDR + j); in xspi_ip_read()
386 while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK)) { in xspi_ip_read()
387 PRA("0x%x", fspi_readl(FSPI_INTR)); in xspi_ip_read()
438 while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPTXWE_MASK) == 0) in xspi_ip_write()
459 while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPTXWE)) in xspi_ip_write()
484 while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK)) in xspi_ip_write()
587 while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0) in xspi_wren()
601 while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0) in fspi_bbluk_er()
612 iprxfcr = fspi_readl(FSPI_IPRXFCR); in fspi_RDSR()
626 while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0) in fspi_RDSR()
630 data = fspi_readl(FSPI_RFDR); in fspi_RDSR()
678 while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0) { in fspi_sec_er()
679 PRA("0x%x", fspi_readl(FSPI_INTR)); in fspi_sec_er()
734 VERBOSE("Flexspi: Register FSPI_MCR0(0x%x) = 0x%08x\n", FSPI_MCR0, fspi_readl(FSPI_MCR0)); in fspi_dump_regs()
735 VERBOSE("Flexspi: Register FSPI_MCR2(0x%x) = 0x%08x\n", FSPI_MCR2, fspi_readl(FSPI_MCR2)); in fspi_dump_regs()
736 VERBOSE("Flexspi: Register FSPI_DLL_A_CR(0x%x) = 0x%08x\n", FSPI_DLLACR, fspi_readl(FSPI_DLLACR)); in fspi_dump_regs()
740 …ster FSPI_AHBRX_BUF0CR0(0x%x) = 0x%08x\n", FSPI_AHBRX_BUF0CR0 + i * 4, fspi_readl((FSPI_AHBRX_BUF0… in fspi_dump_regs()
744 …VERBOSE("Flexspi: Register FSPI_AHBRX_BUF7CR0(0x%x) = 0x%08x\n", FSPI_AHBRX_BUF7CR0, fspi_readl(FS… in fspi_dump_regs()
745 VERBOSE("Flexspi: Register FSPI_AHB_CR(0x%x) \t = 0x%08x\n", FSPI_AHBCR, fspi_readl(FSPI_AHBCR)); in fspi_dump_regs()
749 … Register FSPI_FLSH_A1_CR2,(0x%x) = 0x%08x\n", FSPI_FLSHA1CR2 + i * 4, fspi_readl(FSPI_FLSHA1CR2 +… in fspi_dump_regs()
768 INFO("Flexspi: Default MCR0 = 0x%08x, before reset\n", fspi_readl(FSPI_MCR0)); in fspi_init()
773 while ((fspi_readl(FSPI_MCR0) & FSPI_MCR0_SWRST)) in fspi_init()
784 mcrx = fspi_readl(FSPI_MCR0); in fspi_init()
817 INFO("Flexspi: After MCR0 = 0x%08x,\n", fspi_readl(FSPI_MCR0)); in fspi_init()