Lines Matching refs:reg
615 uint32_t reg; in start_rtdma0_descriptor() local
617 reg = mmio_read_32(RCAR_PRR); in start_rtdma0_descriptor()
618 reg &= (PRR_PRODUCT_MASK | PRR_CUT_MASK); in start_rtdma0_descriptor()
619 if (reg == (PRR_PRODUCT_M3_CUT10)) { in start_rtdma0_descriptor()
671 uint32_t reg; in pfc_init_m3() local
1007 reg = mmio_read_32(PFC_DRVCTRL0); in pfc_init_m3()
1008 reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3) in pfc_init_m3()
1016 pfc_reg_write(PFC_DRVCTRL0, reg); in pfc_init_m3()
1017 reg = mmio_read_32(PFC_DRVCTRL1); in pfc_init_m3()
1018 reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3) in pfc_init_m3()
1026 pfc_reg_write(PFC_DRVCTRL1, reg); in pfc_init_m3()
1027 reg = mmio_read_32(PFC_DRVCTRL2); in pfc_init_m3()
1028 reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7) in pfc_init_m3()
1036 pfc_reg_write(PFC_DRVCTRL2, reg); in pfc_init_m3()
1037 reg = mmio_read_32(PFC_DRVCTRL3); in pfc_init_m3()
1038 reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3) in pfc_init_m3()
1046 pfc_reg_write(PFC_DRVCTRL3, reg); in pfc_init_m3()
1047 reg = mmio_read_32(PFC_DRVCTRL4); in pfc_init_m3()
1048 reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7) in pfc_init_m3()
1056 pfc_reg_write(PFC_DRVCTRL4, reg); in pfc_init_m3()
1057 reg = mmio_read_32(PFC_DRVCTRL5); in pfc_init_m3()
1058 reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7) in pfc_init_m3()
1066 pfc_reg_write(PFC_DRVCTRL5, reg); in pfc_init_m3()
1067 reg = mmio_read_32(PFC_DRVCTRL6); in pfc_init_m3()
1068 reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3) in pfc_init_m3()
1076 pfc_reg_write(PFC_DRVCTRL6, reg); in pfc_init_m3()
1077 reg = mmio_read_32(PFC_DRVCTRL7); in pfc_init_m3()
1078 reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3) in pfc_init_m3()
1086 pfc_reg_write(PFC_DRVCTRL7, reg); in pfc_init_m3()
1087 reg = mmio_read_32(PFC_DRVCTRL8); in pfc_init_m3()
1088 reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7) in pfc_init_m3()
1096 pfc_reg_write(PFC_DRVCTRL8, reg); in pfc_init_m3()
1097 reg = mmio_read_32(PFC_DRVCTRL9); in pfc_init_m3()
1098 reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7) in pfc_init_m3()
1106 pfc_reg_write(PFC_DRVCTRL9, reg); in pfc_init_m3()
1107 reg = mmio_read_32(PFC_DRVCTRL10); in pfc_init_m3()
1108 reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7) in pfc_init_m3()
1116 pfc_reg_write(PFC_DRVCTRL10, reg); in pfc_init_m3()
1117 reg = mmio_read_32(PFC_DRVCTRL11); in pfc_init_m3()
1118 reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3) in pfc_init_m3()
1126 pfc_reg_write(PFC_DRVCTRL11, reg); in pfc_init_m3()
1127 reg = mmio_read_32(PFC_DRVCTRL12); in pfc_init_m3()
1128 reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3) in pfc_init_m3()
1132 pfc_reg_write(PFC_DRVCTRL12, reg); in pfc_init_m3()
1133 reg = mmio_read_32(PFC_DRVCTRL13); in pfc_init_m3()
1134 reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3) in pfc_init_m3()
1142 pfc_reg_write(PFC_DRVCTRL13, reg); in pfc_init_m3()
1143 reg = mmio_read_32(PFC_DRVCTRL14); in pfc_init_m3()
1144 reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7) in pfc_init_m3()
1152 pfc_reg_write(PFC_DRVCTRL14, reg); in pfc_init_m3()
1153 reg = mmio_read_32(PFC_DRVCTRL15); in pfc_init_m3()
1154 reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5) in pfc_init_m3()
1162 pfc_reg_write(PFC_DRVCTRL15, reg); in pfc_init_m3()
1163 reg = mmio_read_32(PFC_DRVCTRL16); in pfc_init_m3()
1164 reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7) in pfc_init_m3()
1172 pfc_reg_write(PFC_DRVCTRL16, reg); in pfc_init_m3()
1173 reg = mmio_read_32(PFC_DRVCTRL17); in pfc_init_m3()
1174 reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7) in pfc_init_m3()
1182 pfc_reg_write(PFC_DRVCTRL17, reg); in pfc_init_m3()
1183 reg = mmio_read_32(PFC_DRVCTRL18); in pfc_init_m3()
1184 reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7) in pfc_init_m3()
1192 pfc_reg_write(PFC_DRVCTRL18, reg); in pfc_init_m3()
1193 reg = mmio_read_32(PFC_DRVCTRL19); in pfc_init_m3()
1194 reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7) in pfc_init_m3()
1202 pfc_reg_write(PFC_DRVCTRL19, reg); in pfc_init_m3()
1203 reg = mmio_read_32(PFC_DRVCTRL20); in pfc_init_m3()
1204 reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7) in pfc_init_m3()
1212 pfc_reg_write(PFC_DRVCTRL20, reg); in pfc_init_m3()
1213 reg = mmio_read_32(PFC_DRVCTRL21); in pfc_init_m3()
1214 reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7) in pfc_init_m3()
1222 pfc_reg_write(PFC_DRVCTRL21, reg); in pfc_init_m3()
1223 reg = mmio_read_32(PFC_DRVCTRL22); in pfc_init_m3()
1224 reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7) in pfc_init_m3()
1232 pfc_reg_write(PFC_DRVCTRL22, reg); in pfc_init_m3()
1233 reg = mmio_read_32(PFC_DRVCTRL23); in pfc_init_m3()
1234 reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7) in pfc_init_m3()
1242 pfc_reg_write(PFC_DRVCTRL23, reg); in pfc_init_m3()
1243 reg = mmio_read_32(PFC_DRVCTRL24); in pfc_init_m3()
1244 reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7) in pfc_init_m3()
1251 pfc_reg_write(PFC_DRVCTRL24, reg); in pfc_init_m3()