Lines Matching refs:reg
581 uint32_t reg; in pfc_init_m3n() local
914 reg = mmio_read_32(PFC_DRVCTRL0); in pfc_init_m3n()
915 reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3) in pfc_init_m3n()
923 pfc_reg_write(PFC_DRVCTRL0, reg); in pfc_init_m3n()
924 reg = mmio_read_32(PFC_DRVCTRL1); in pfc_init_m3n()
925 reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3) in pfc_init_m3n()
933 pfc_reg_write(PFC_DRVCTRL1, reg); in pfc_init_m3n()
934 reg = mmio_read_32(PFC_DRVCTRL2); in pfc_init_m3n()
935 reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7) in pfc_init_m3n()
943 pfc_reg_write(PFC_DRVCTRL2, reg); in pfc_init_m3n()
944 reg = mmio_read_32(PFC_DRVCTRL3); in pfc_init_m3n()
945 reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3) in pfc_init_m3n()
953 pfc_reg_write(PFC_DRVCTRL3, reg); in pfc_init_m3n()
954 reg = mmio_read_32(PFC_DRVCTRL4); in pfc_init_m3n()
955 reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7) in pfc_init_m3n()
963 pfc_reg_write(PFC_DRVCTRL4, reg); in pfc_init_m3n()
964 reg = mmio_read_32(PFC_DRVCTRL5); in pfc_init_m3n()
965 reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7) in pfc_init_m3n()
973 pfc_reg_write(PFC_DRVCTRL5, reg); in pfc_init_m3n()
974 reg = mmio_read_32(PFC_DRVCTRL6); in pfc_init_m3n()
975 reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3) in pfc_init_m3n()
983 pfc_reg_write(PFC_DRVCTRL6, reg); in pfc_init_m3n()
984 reg = mmio_read_32(PFC_DRVCTRL7); in pfc_init_m3n()
985 reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3) in pfc_init_m3n()
993 pfc_reg_write(PFC_DRVCTRL7, reg); in pfc_init_m3n()
994 reg = mmio_read_32(PFC_DRVCTRL8); in pfc_init_m3n()
995 reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7) in pfc_init_m3n()
1003 pfc_reg_write(PFC_DRVCTRL8, reg); in pfc_init_m3n()
1004 reg = mmio_read_32(PFC_DRVCTRL9); in pfc_init_m3n()
1005 reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7) in pfc_init_m3n()
1013 pfc_reg_write(PFC_DRVCTRL9, reg); in pfc_init_m3n()
1014 reg = mmio_read_32(PFC_DRVCTRL10); in pfc_init_m3n()
1015 reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7) in pfc_init_m3n()
1023 pfc_reg_write(PFC_DRVCTRL10, reg); in pfc_init_m3n()
1024 reg = mmio_read_32(PFC_DRVCTRL11); in pfc_init_m3n()
1025 reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3) in pfc_init_m3n()
1033 pfc_reg_write(PFC_DRVCTRL11, reg); in pfc_init_m3n()
1034 reg = mmio_read_32(PFC_DRVCTRL12); in pfc_init_m3n()
1035 reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3) in pfc_init_m3n()
1039 pfc_reg_write(PFC_DRVCTRL12, reg); in pfc_init_m3n()
1040 reg = mmio_read_32(PFC_DRVCTRL13); in pfc_init_m3n()
1041 reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3) in pfc_init_m3n()
1049 pfc_reg_write(PFC_DRVCTRL13, reg); in pfc_init_m3n()
1050 reg = mmio_read_32(PFC_DRVCTRL14); in pfc_init_m3n()
1051 reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7) in pfc_init_m3n()
1059 pfc_reg_write(PFC_DRVCTRL14, reg); in pfc_init_m3n()
1060 reg = mmio_read_32(PFC_DRVCTRL15); in pfc_init_m3n()
1061 reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5) in pfc_init_m3n()
1069 pfc_reg_write(PFC_DRVCTRL15, reg); in pfc_init_m3n()
1070 reg = mmio_read_32(PFC_DRVCTRL16); in pfc_init_m3n()
1071 reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7) in pfc_init_m3n()
1079 pfc_reg_write(PFC_DRVCTRL16, reg); in pfc_init_m3n()
1080 reg = mmio_read_32(PFC_DRVCTRL17); in pfc_init_m3n()
1081 reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7) in pfc_init_m3n()
1089 pfc_reg_write(PFC_DRVCTRL17, reg); in pfc_init_m3n()
1090 reg = mmio_read_32(PFC_DRVCTRL18); in pfc_init_m3n()
1091 reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7) in pfc_init_m3n()
1099 pfc_reg_write(PFC_DRVCTRL18, reg); in pfc_init_m3n()
1100 reg = mmio_read_32(PFC_DRVCTRL19); in pfc_init_m3n()
1101 reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7) in pfc_init_m3n()
1109 pfc_reg_write(PFC_DRVCTRL19, reg); in pfc_init_m3n()
1110 reg = mmio_read_32(PFC_DRVCTRL20); in pfc_init_m3n()
1111 reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7) in pfc_init_m3n()
1119 pfc_reg_write(PFC_DRVCTRL20, reg); in pfc_init_m3n()
1120 reg = mmio_read_32(PFC_DRVCTRL21); in pfc_init_m3n()
1121 reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7) in pfc_init_m3n()
1129 pfc_reg_write(PFC_DRVCTRL21, reg); in pfc_init_m3n()
1130 reg = mmio_read_32(PFC_DRVCTRL22); in pfc_init_m3n()
1131 reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7) in pfc_init_m3n()
1139 pfc_reg_write(PFC_DRVCTRL22, reg); in pfc_init_m3n()
1140 reg = mmio_read_32(PFC_DRVCTRL23); in pfc_init_m3n()
1141 reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7) in pfc_init_m3n()
1149 pfc_reg_write(PFC_DRVCTRL23, reg); in pfc_init_m3n()
1150 reg = mmio_read_32(PFC_DRVCTRL24); in pfc_init_m3n()
1151 reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7) in pfc_init_m3n()
1158 pfc_reg_write(PFC_DRVCTRL24, reg); in pfc_init_m3n()