Lines Matching refs:VERBOSE
308 VERBOSE("init %s\n", ddr_registers[type].name); in set_reg()
332 VERBOSE(" > [0x%lx] pgsr = 0x%x &\n", in stm32mp1_ddrphy_idone_wait()
340 VERBOSE("DQS Gate Trainig Error\n"); in stm32mp1_ddrphy_idone_wait()
345 VERBOSE("DQS Gate Trainig Intermittent Error\n"); in stm32mp1_ddrphy_idone_wait()
350 VERBOSE("DQS Drift Error\n"); in stm32mp1_ddrphy_idone_wait()
355 VERBOSE("Read Valid Training Error\n"); in stm32mp1_ddrphy_idone_wait()
360 VERBOSE("Read Valid Training Intermittent Error\n"); in stm32mp1_ddrphy_idone_wait()
364 VERBOSE("\n[0x%lx] pgsr = 0x%x\n", in stm32mp1_ddrphy_idone_wait()
373 VERBOSE("[0x%lx] pir = 0x%x -> 0x%x\n", in stm32mp1_ddrphy_init()
388 VERBOSE("[0x%lx] swctl = 0x%x\n", in stm32mp1_start_sw_done()
399 VERBOSE("[0x%lx] swctl = 0x%x\n", in stm32mp1_wait_sw_done_ack()
405 VERBOSE("[0x%lx] swstat = 0x%x ", in stm32mp1_wait_sw_done_ack()
412 VERBOSE("[0x%lx] swstat = 0x%x\n", in stm32mp1_wait_sw_done_ack()
431 VERBOSE("[0x%lx] stat = 0x%x\n", in stm32mp1_wait_operating_mode()
461 VERBOSE("[0x%lx] stat = 0x%x\n", in stm32mp1_wait_operating_mode()
471 VERBOSE("MRS: %d = %x\n", addr, data); in stm32mp1_mode_register_write()
493 VERBOSE("[0x%lx] mrctrl0 = 0x%x (0x%x)\n", in stm32mp1_mode_register_write()
497 VERBOSE("[0x%lx] mrctrl1 = 0x%x\n", in stm32mp1_mode_register_write()
516 VERBOSE("[0x%lx] mrctrl0 = 0x%x\n", in stm32mp1_mode_register_write()
527 VERBOSE("mr1: 0x%x\n", mr1); in stm32mp1_ddr3_dll_off()
528 VERBOSE("mr2: 0x%x\n", mr2); in stm32mp1_ddr3_dll_off()
535 VERBOSE("[0x%lx] dbg1 = 0x%x\n", in stm32mp1_ddr3_dll_off()
549 VERBOSE("[0x%lx] dbgcam = 0x%x\n", in stm32mp1_ddr3_dll_off()
596 VERBOSE("[0x%lx] pwrctl = 0x%x\n", in stm32mp1_ddr3_dll_off()
615 VERBOSE("[0x%lx] mstr = 0x%x\n", in stm32mp1_ddr3_dll_off()
667 VERBOSE("[0x%lx] dbg1 = 0x%x\n", in stm32mp1_ddr3_dll_off()
730 VERBOSE("name = %s\n", config->info.name); in stm32mp1_ddr_init()
731 VERBOSE("speed = %d kHz\n", config->info.speed); in stm32mp1_ddr_init()
732 VERBOSE("size = 0x%x\n", config->info.size); in stm32mp1_ddr_init()
772 VERBOSE("[0x%lx] dfimisc = 0x%x\n", in stm32mp1_ddr_init()
782 VERBOSE("deactivate DLL OFF in mstr\n"); in stm32mp1_ddr_init()
785 VERBOSE("[0x%lx] mstr = 0x%x\n", in stm32mp1_ddr_init()
797 VERBOSE("[0x%lx] init0 = 0x%x\n", in stm32mp1_ddr_init()
820 VERBOSE("deactivate DLL OFF in mr1\n"); in stm32mp1_ddr_init()
822 VERBOSE("[0x%lx] mr1 = 0x%x\n", in stm32mp1_ddr_init()
856 VERBOSE("[0x%lx] dfimisc = 0x%x\n", in stm32mp1_ddr_init()
875 VERBOSE("DDR DQS training : "); in stm32mp1_ddr_init()
910 VERBOSE("[0x%lx] pctrl_0 = 0x%x\n", in stm32mp1_ddr_init()
917 VERBOSE("[0x%lx] pctrl_1 = 0x%x\n", in stm32mp1_ddr_init()