Lines Matching refs:_h
19 #define SMC_RET0(_h) { \ argument
20 return (uint64_t) (_h); \
22 #define SMC_RET1(_h, _x0) { \ argument
23 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X0), (_x0)); \
24 SMC_RET0(_h); \
26 #define SMC_RET2(_h, _x0, _x1) { \ argument
27 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X1), (_x1)); \
28 SMC_RET1(_h, (_x0)); \
30 #define SMC_RET3(_h, _x0, _x1, _x2) { \ argument
31 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X2), (_x2)); \
32 SMC_RET2(_h, (_x0), (_x1)); \
34 #define SMC_RET4(_h, _x0, _x1, _x2, _x3) { \ argument
35 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X3), (_x3)); \
36 SMC_RET3(_h, (_x0), (_x1), (_x2)); \
38 #define SMC_RET5(_h, _x0, _x1, _x2, _x3, _x4) { \ argument
39 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X4), (_x4)); \
40 SMC_RET4(_h, (_x0), (_x1), (_x2), (_x3)); \
42 #define SMC_RET6(_h, _x0, _x1, _x2, _x3, _x4, _x5) { \ argument
43 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X5), (_x5)); \
44 SMC_RET5(_h, (_x0), (_x1), (_x2), (_x3), (_x4)); \
46 #define SMC_RET7(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6) { \ argument
47 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X6), (_x6)); \
48 SMC_RET6(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5)); \
50 #define SMC_RET8(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6, _x7) { \ argument
51 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X7), (_x7)); \
52 SMC_RET7(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5), (_x6)); \
59 #define SMC_GET_GP(_h, _g) \ argument
60 read_ctx_reg((get_gpregs_ctx(_h)), (_g))
61 #define SMC_SET_GP(_h, _g, _v) \ argument
62 write_ctx_reg((get_gpregs_ctx(_h)), (_g), (_v))
68 #define SMC_GET_EL3(_h, _e) \ argument
69 read_ctx_reg((get_el3state_ctx(_h)), (_e))
70 #define SMC_SET_EL3(_h, _e, _v) \ argument
71 write_ctx_reg((get_el3state_ctx(_h)), (_e), (_v))