Lines Matching refs:GENMASK
258 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
264 #define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0)
267 #define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4)
277 #define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12)
287 #define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16)
294 #define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16)
297 #define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK GENMASK(31, 30)
307 #define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8)
308 #define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0)
358 #define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7)
362 #define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25)
377 #define DDRPHYC_PTR0_TDLLSRST_MASK GENMASK(5, 0)
379 #define DDRPHYC_PTR0_TDLLLOCK_MASK GENMASK(17, 6)
381 #define DDRPHYC_PTR0_TITMSRST_MASK GENMASK(21, 18)
385 #define DDRPHYC_ACIOCR_CKPDD_MASK GENMASK(10, 8)
387 #define DDRPHYC_ACIOCR_CKPDR_MASK GENMASK(13, 11)
389 #define DDRPHYC_ACIOCR_CSPDD_MASK GENMASK(21, 18)
397 #define DDRPHYC_DSGCR_CKEPDD_MASK GENMASK(19, 16)
399 #define DDRPHYC_DSGCR_ODTPDD_MASK GENMASK(23, 20)
403 #define DDRPHYC_ZQ0CRN_ZDATA_MASK GENMASK(27, 0)
412 #define DDRPHYC_DXNDLLCR_SDPHASE_MASK GENMASK(17, 14)