Lines Matching refs:uint32_t
14 uint32_t mstr ; /* 0x0 Master */
15 uint32_t stat; /* 0x4 Operating Mode Status */
17 uint32_t mrctrl0; /* 0x10 Control 0 */
18 uint32_t mrctrl1; /* 0x14 Control 1 */
19 uint32_t mrstat; /* 0x18 Status */
20 uint32_t reserved01c; /* 0x1c */
21 uint32_t derateen; /* 0x20 Temperature Derate Enable */
22 uint32_t derateint; /* 0x24 Temperature Derate Interval */
24 uint32_t pwrctl; /* 0x30 Low Power Control */
25 uint32_t pwrtmg; /* 0x34 Low Power Timing */
26 uint32_t hwlpctl; /* 0x38 Hardware Low Power Control */
28 uint32_t rfshctl0; /* 0x50 Refresh Control 0 */
29 uint32_t reserved054; /* 0x54 Refresh Control 1 */
30 uint32_t reserved058; /* 0x58 Refresh Control 2 */
31 uint32_t reserved05C;
32 uint32_t rfshctl3; /* 0x60 Refresh Control 0 */
33 uint32_t rfshtmg; /* 0x64 Refresh Timing */
35 uint32_t crcparctl0; /* 0xc0 CRC Parity Control0 */
36 uint32_t reserved0c4; /* 0xc4 CRC Parity Control1 */
37 uint32_t reserved0c8; /* 0xc8 CRC Parity Control2 */
38 uint32_t crcparstat; /* 0xcc CRC Parity Status */
39 uint32_t init0; /* 0xd0 SDRAM Initialization 0 */
40 uint32_t init1; /* 0xd4 SDRAM Initialization 1 */
41 uint32_t init2; /* 0xd8 SDRAM Initialization 2 */
42 uint32_t init3; /* 0xdc SDRAM Initialization 3 */
43 uint32_t init4; /* 0xe0 SDRAM Initialization 4 */
44 uint32_t init5; /* 0xe4 SDRAM Initialization 5 */
45 uint32_t reserved0e8;
46 uint32_t reserved0ec;
47 uint32_t dimmctl; /* 0xf0 DIMM Control */
49 uint32_t dramtmg0; /* 0x100 SDRAM Timing 0 */
50 uint32_t dramtmg1; /* 0x104 SDRAM Timing 1 */
51 uint32_t dramtmg2; /* 0x108 SDRAM Timing 2 */
52 uint32_t dramtmg3; /* 0x10c SDRAM Timing 3 */
53 uint32_t dramtmg4; /* 0x110 SDRAM Timing 4 */
54 uint32_t dramtmg5; /* 0x114 SDRAM Timing 5 */
55 uint32_t dramtmg6; /* 0x118 SDRAM Timing 6 */
56 uint32_t dramtmg7; /* 0x11c SDRAM Timing 7 */
57 uint32_t dramtmg8; /* 0x120 SDRAM Timing 8 */
59 uint32_t dramtmg14; /* 0x138 SDRAM Timing 14 */
60 uint32_t dramtmg15; /* 0x13C SDRAM Timing 15 */
62 uint32_t zqctl0; /* 0x180 ZQ Control 0 */
63 uint32_t zqctl1; /* 0x184 ZQ Control 1 */
64 uint32_t zqctl2; /* 0x188 ZQ Control 2 */
65 uint32_t zqstat; /* 0x18c ZQ Status */
66 uint32_t dfitmg0; /* 0x190 DFI Timing 0 */
67 uint32_t dfitmg1; /* 0x194 DFI Timing 1 */
68 uint32_t dfilpcfg0; /* 0x198 DFI Low Power Configuration 0 */
69 uint32_t reserved19c;
70 uint32_t dfiupd0; /* 0x1a0 DFI Update 0 */
71 uint32_t dfiupd1; /* 0x1a4 DFI Update 1 */
72 uint32_t dfiupd2; /* 0x1a8 DFI Update 2 */
73 uint32_t reserved1ac;
74 uint32_t dfimisc; /* 0x1b0 DFI Miscellaneous Control */
76 uint32_t dfistat; /* 0x1bc DFI Miscellaneous Control */
78 uint32_t dfiphymstr; /* 0x1c4 DFI PHY Master interface */
80 uint32_t addrmap1; /* 0x204 Address Map 1 */
81 uint32_t addrmap2; /* 0x208 Address Map 2 */
82 uint32_t addrmap3; /* 0x20c Address Map 3 */
83 uint32_t addrmap4; /* 0x210 Address Map 4 */
84 uint32_t addrmap5; /* 0x214 Address Map 5 */
85 uint32_t addrmap6; /* 0x218 Address Map 6 */
87 uint32_t addrmap9; /* 0x224 Address Map 9 */
88 uint32_t addrmap10; /* 0x228 Address Map 10 */
89 uint32_t addrmap11; /* 0x22C Address Map 11 */
91 uint32_t odtcfg; /* 0x240 ODT Configuration */
92 uint32_t odtmap; /* 0x244 ODT/Rank Map */
94 uint32_t sched; /* 0x250 Scheduler Control */
95 uint32_t sched1; /* 0x254 Scheduler Control 1 */
96 uint32_t reserved258;
97 uint32_t perfhpr1; /* 0x25c High Priority Read CAM 1 */
98 uint32_t reserved260;
99 uint32_t perflpr1; /* 0x264 Low Priority Read CAM 1 */
100 uint32_t reserved268;
101 uint32_t perfwr1; /* 0x26c Write CAM 1 */
103 uint32_t dbg0; /* 0x300 Debug 0 */
104 uint32_t dbg1; /* 0x304 Debug 1 */
105 uint32_t dbgcam; /* 0x308 CAM Debug */
106 uint32_t dbgcmd; /* 0x30c Command Debug */
107 uint32_t dbgstat; /* 0x310 Status Debug */
109 uint32_t swctl; /* 0x320 Software Programming Control Enable */
110 uint32_t swstat; /* 0x324 Software Programming Control Status */
112 uint32_t poisoncfg; /* 0x36c AXI Poison Configuration Register */
113 uint32_t poisonstat; /* 0x370 AXI Poison Status Register */
117 uint32_t pstat; /* 0x3fc Port Status */
118 uint32_t pccfg; /* 0x400 Port Common Configuration */
121 uint32_t pcfgr_0; /* 0x404 Configuration Read */
122 uint32_t pcfgw_0; /* 0x408 Configuration Write */
124 uint32_t pctrl_0; /* 0x490 Port Control Register */
125 uint32_t pcfgqos0_0; /* 0x494 Read QoS Configuration 0 */
126 uint32_t pcfgqos1_0; /* 0x498 Read QoS Configuration 1 */
127 uint32_t pcfgwqos0_0; /* 0x49c Write QoS Configuration 0 */
128 uint32_t pcfgwqos1_0; /* 0x4a0 Write QoS Configuration 1 */
132 uint32_t pcfgr_1; /* 0x4b4 Configuration Read */
133 uint32_t pcfgw_1; /* 0x4b8 Configuration Write */
135 uint32_t pctrl_1; /* 0x540 Port 2 Control Register */
136 uint32_t pcfgqos0_1; /* 0x544 Read QoS Configuration 0 */
137 uint32_t pcfgqos1_1; /* 0x548 Read QoS Configuration 1 */
138 uint32_t pcfgwqos0_1; /* 0x54c Write QoS Configuration 0 */
139 uint32_t pcfgwqos1_1; /* 0x550 Write QoS Configuration 1 */
144 uint32_t ridr; /* 0x00 R Revision Identification */
145 uint32_t pir; /* 0x04 R/W PHY Initialization */
146 uint32_t pgcr; /* 0x08 R/W PHY General Configuration */
147 uint32_t pgsr; /* 0x0C PHY General Status */
148 uint32_t dllgcr; /* 0x10 R/W DLL General Control */
149 uint32_t acdllcr; /* 0x14 R/W AC DLL Control */
150 uint32_t ptr0; /* 0x18 R/W PHY Timing 0 */
151 uint32_t ptr1; /* 0x1C R/W PHY Timing 1 */
152 uint32_t ptr2; /* 0x20 R/W PHY Timing 2 */
153 uint32_t aciocr; /* 0x24 AC I/O Configuration */
154 uint32_t dxccr; /* 0x28 DATX8 Common Configuration */
155 uint32_t dsgcr; /* 0x2C DDR System General Configuration */
156 uint32_t dcr; /* 0x30 DRAM Configuration */
157 uint32_t dtpr0; /* 0x34 DRAM Timing Parameters0 */
158 uint32_t dtpr1; /* 0x38 DRAM Timing Parameters1 */
159 uint32_t dtpr2; /* 0x3C DRAM Timing Parameters2 */
160 uint32_t mr0; /* 0x40 Mode 0 */
161 uint32_t mr1; /* 0x44 Mode 1 */
162 uint32_t mr2; /* 0x48 Mode 2 */
163 uint32_t mr3; /* 0x4C Mode 3 */
164 uint32_t odtcr; /* 0x50 ODT Configuration */
165 uint32_t dtar; /* 0x54 data training address */
166 uint32_t dtdr0; /* 0x58 */
167 uint32_t dtdr1; /* 0x5c */
169 uint32_t dcuar; /* 0xc0 Address */
170 uint32_t dcudr; /* 0xc4 DCU Data */
171 uint32_t dcurr; /* 0xc8 DCU Run */
172 uint32_t dculr; /* 0xcc DCU Loop */
173 uint32_t dcugcr; /* 0xd0 DCU General Configuration */
174 uint32_t dcutpr; /* 0xd4 DCU Timing Parameters */
175 uint32_t dcusr0; /* 0xd8 DCU Status 0 */
176 uint32_t dcusr1; /* 0xdc DCU Status 1 */
178 uint32_t bistrr; /* 0x100 BIST Run */
179 uint32_t bistmskr0; /* 0x104 BIST Mask 0 */
180 uint32_t bistmskr1; /* 0x108 BIST Mask 0 */
181 uint32_t bistwcr; /* 0x10c BIST Word Count */
182 uint32_t bistlsr; /* 0x110 BIST LFSR Seed */
183 uint32_t bistar0; /* 0x114 BIST Address 0 */
184 uint32_t bistar1; /* 0x118 BIST Address 1 */
185 uint32_t bistar2; /* 0x11c BIST Address 2 */
186 uint32_t bistupdr; /* 0x120 BIST User Data Pattern */
187 uint32_t bistgsr; /* 0x124 BIST General Status */
188 uint32_t bistwer; /* 0x128 BIST Word Error */
189 uint32_t bistber0; /* 0x12c BIST Bit Error 0 */
190 uint32_t bistber1; /* 0x130 BIST Bit Error 1 */
191 uint32_t bistber2; /* 0x134 BIST Bit Error 2 */
192 uint32_t bistwcsr; /* 0x138 BIST Word Count Status */
193 uint32_t bistfwr0; /* 0x13c BIST Fail Word 0 */
194 uint32_t bistfwr1; /* 0x140 BIST Fail Word 1 */
196 uint32_t gpr0; /* 0x178 General Purpose 0 (GPR0) */
197 uint32_t gpr1; /* 0x17C General Purpose 1 (GPR1) */
198 uint32_t zq0cr0; /* 0x180 zq 0 control 0 */
199 uint32_t zq0cr1; /* 0x184 zq 0 control 1 */
200 uint32_t zq0sr0; /* 0x188 zq 0 status 0 */
201 uint32_t zq0sr1; /* 0x18C zq 0 status 1 */
203 uint32_t dx0gcr; /* 0x1c0 Byte lane 0 General Configuration */
204 uint32_t dx0gsr0; /* 0x1c4 Byte lane 0 General Status 0 */
205 uint32_t dx0gsr1; /* 0x1c8 Byte lane 0 General Status 1 */
206 uint32_t dx0dllcr; /* 0x1cc Byte lane 0 DLL Control */
207 uint32_t dx0dqtr; /* 0x1d0 Byte lane 0 DQ Timing */
208 uint32_t dx0dqstr; /* 0x1d4 Byte lane 0 DQS Timing */
210 uint32_t dx1gcr; /* 0x200 Byte lane 1 General Configuration */
211 uint32_t dx1gsr0; /* 0x204 Byte lane 1 General Status 0 */
212 uint32_t dx1gsr1; /* 0x208 Byte lane 1 General Status 1 */
213 uint32_t dx1dllcr; /* 0x20c Byte lane 1 DLL Control */
214 uint32_t dx1dqtr; /* 0x210 Byte lane 1 DQ Timing */
215 uint32_t dx1dqstr; /* 0x214 Byte lane 1 QS Timing */
217 uint32_t dx2gcr; /* 0x240 Byte lane 2 General Configuration */
218 uint32_t dx2gsr0; /* 0x244 Byte lane 2 General Status 0 */
219 uint32_t dx2gsr1; /* 0x248 Byte lane 2 General Status 1 */
220 uint32_t dx2dllcr; /* 0x24c Byte lane 2 DLL Control */
221 uint32_t dx2dqtr; /* 0x250 Byte lane 2 DQ Timing */
222 uint32_t dx2dqstr; /* 0x254 Byte lane 2 QS Timing */
224 uint32_t dx3gcr; /* 0x280 Byte lane 3 General Configuration */
225 uint32_t dx3gsr0; /* 0x284 Byte lane 3 General Status 0 */
226 uint32_t dx3gsr1; /* 0x288 Byte lane 3 General Status 1 */
227 uint32_t dx3dllcr; /* 0x28c Byte lane 3 DLL Control */
228 uint32_t dx3dqtr; /* 0x290 Byte lane 3 DQ Timing */
229 uint32_t dx3dqstr; /* 0x294 Byte lane 3 QS Timing */