Lines Matching refs:x1
67 cmp x1, xzr /* enable/disable check */
79 adr x1, cortex_a76_disable_wa_cve_2018_3639
80 csel x1, x1, x0, eq
81 str x1, [sp, #CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_DISABLE]
84 orr x1, x2, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
86 csel x3, x3, x1, eq
215 mrs x1, CORTEX_A76_CPUACTLR_EL1
216 orr x1, x1 ,#CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION
217 msr CORTEX_A76_CPUACTLR_EL1, x1
224 mov x1, #0x10
243 mrs x1, CORTEX_A76_CPUACTLR2_EL1
244 orr x1, x1 ,#(1 << 59)
245 msr CORTEX_A76_CPUACTLR2_EL1, x1
252 mov x1, #0x20
271 mrs x1, CORTEX_A76_CPUECTLR_EL1
272 orr x1, x1, #CORTEX_A76_CPUECTLR_EL1_WS_THR_L2
273 msr CORTEX_A76_CPUECTLR_EL1, x1
280 mov x1, #0x20
299 mrs x1, CORTEX_A76_CPUACTLR3_EL1
300 orr x1, x1, CORTEX_A76_CPUACTLR3_EL1_BIT_10
301 msr CORTEX_A76_CPUACTLR3_EL1, x1
308 mov x1, #0x30
327 mrs x1, CORTEX_A76_CPUECTLR_EL1
328 orr x1, x1, CORTEX_A76_CPUECTLR_EL1_BIT_51
329 msr CORTEX_A76_CPUECTLR_EL1, x1
336 mov x1, #0x30
352 mov x1, #0x30
370 mrs x1, CORTEX_A76_CPUACTLR2_EL1
371 orr x1, x1, CORTEX_A76_CPUACTLR2_EL1_BIT_2
372 msr CORTEX_A76_CPUACTLR2_EL1, x1
380 mov x1, #0x40
410 mrs x1, CORTEX_A76_CPUACTLR_EL1
411 orr x1, x1, #CORTEX_A76_CPUACTLR_EL1_BIT_13
412 msr CORTEX_A76_CPUACTLR_EL1, x1
419 mov x1, #0x30
424 mov x1, #0x30
429 mov x1, #0x40
483 mov x1, #0x30
517 mov x1, #0x30