Lines Matching refs:UL
20 #define AML_HDCP_RX_BASE UL(0xFFE0D000)
21 #define AML_HDCP_RX_SIZE UL(0x00002000)
23 #define AML_HDCP_TX_BASE UL(0xFFE01000)
24 #define AML_HDCP_TX_SIZE UL(0x00001000)
26 #define AML_NS_SHARE_MEM_BASE UL(0x05000000)
27 #define AML_NS_SHARE_MEM_SIZE UL(0x00100000)
29 #define AML_SEC_SHARE_MEM_BASE UL(0x05200000)
30 #define AML_SEC_SHARE_MEM_SIZE UL(0x00100000)
32 #define AML_GIC_DEVICE_BASE UL(0xFFC00000)
33 #define AML_GIC_DEVICE_SIZE UL(0x00008000)
35 #define AML_NSDRAM0_BASE UL(0x01000000)
36 #define AML_NSDRAM0_SIZE UL(0x0F000000)
38 #define BL31_BASE UL(0x05100000)
39 #define BL31_SIZE UL(0x00100000)
43 #define AML_SHARE_MEM_INPUT_BASE UL(0x050FE000)
44 #define AML_SHARE_MEM_OUTPUT_BASE UL(0x050FF000)
46 #define AML_SEC_DEVICE0_BASE UL(0xFFD00000)
47 #define AML_SEC_DEVICE0_SIZE UL(0x00026000)
49 #define AML_SEC_DEVICE1_BASE UL(0xFF800000)
50 #define AML_SEC_DEVICE1_SIZE UL(0x0000A000)
52 #define AML_TZRAM_BASE UL(0xFFFA0000)
53 #define AML_TZRAM_SIZE UL(0x00048000)
56 #define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xFFFE7800)
57 #define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xFFFE7A00)
58 #define AML_PSCI_MAILBOX_BASE UL(0xFFFE7F00)
60 #define AML_SEC_DEVICE2_BASE UL(0xFF620000)
61 #define AML_SEC_DEVICE2_SIZE UL(0x00028000)
66 #define AML_GICD_BASE UL(0xFFC01000)
67 #define AML_GICC_BASE UL(0xFFC02000)
84 #define AML_UART0_AO_BASE UL(0xFF803000)
91 #define AML_AO_TIMESTAMP_CNTL UL(0xFF8000B4)
93 #define AML_SYS_CPU_CFG7 UL(0xFF634664)
95 #define AML_AO_RTI_STATUS_REG3 UL(0xFF80001C)
96 #define AML_AO_RTI_SCP_STAT UL(0xFF80023C)
103 #define AML_HIU_MAILBOX_SET_0 UL(0xFF63C404)
104 #define AML_HIU_MAILBOX_STAT_0 UL(0xFF63C408)
105 #define AML_HIU_MAILBOX_CLR_0 UL(0xFF63C40C)
106 #define AML_HIU_MAILBOX_SET_3 UL(0xFF63C428)
107 #define AML_HIU_MAILBOX_STAT_3 UL(0xFF63C42C)
108 #define AML_HIU_MAILBOX_CLR_3 UL(0xFF63C430)
110 #define AML_SHA_DMA_BASE UL(0xFF63E000)